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3.1 More on Verilog
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Lab 3: Decoders and
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2 Lab
3 Supplementary Material
Subsections
3.1 More on Verilog
3.1.1 Three-State Gates
3.1.2 Logic Levels
3.2 Verilog - Behavioral Modeling
3.2.1
always
and
reg
3.2.2
if-else
Statements
3.2.3
case
Statements
Copyright © 2008, Electrical Engineering Department, New Mexico Tech
Last Modified 2008-10-10
