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Up: Lab 9: Computer Control Previous: 1 Prelab

2 Lab

  1. Assign op codes to each instruction in the instruction set.
  2. Write a Verilog program to implement the control unit.
  3. Simulate the control unit in Altera. What happens when RESET is low? Test with different values for INST and check that the control unit cycles through the appropriate states for that instruction and that the control signals are what you expect. Test the JCS command both when the carry is set and when the carry is not set.

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Last Modified 2008-11-14