module control (
	input [7:0] inst, 
	input z_in, c_in, 
	input sys_clock, reset, 
	output reg [3:0] alu_ctrl,
	output reg data_mux_sel,
	output reg [1:0] addr_mux_sel,
	output reg x_load, a_load, pc_inc, pc_load, ir_load, mar_load,
	output reg z_load, c_load, 
	output reg mem_w
);

`include "constants.v"

parameter RST = 2'b00,
          FETCH   = 2'b01,
          EX1   = 2'b10,
          EX2   = 2'b11;

reg [2:0] state;

always @(posedge sys_clock or negedge reset)
	if (reset == 0) state <= RST;
	else
		case(state)
			RST: state <= FETCH;
			FETCH: state <= EX1;
			EX1:
				case (inst)
					NOP:  		state <= FETCH;
					LDAA: 		state <= EX2;
					LDAA_IMM: 	state <= FETCH;
					STAA:		state <= EX2;
                .
                .
                .

                // add more instructions

                .
                .
                .


				endcase

                .
                .
                .

                // add more instructions

                .
                .
                .

		endcase
	
	always @ (state or inst or c_in or z_in)
		begin
                .
                .
                .

                // add some defaults

                .
                .
                .

			case (state)

                .
                .
                .

                // add more instructions

                .
                .
                .

				EX1:
				case (inst)
					LDAA_IMM:
					begin
						addr_mux_sel = PC_SEL;
						alu_ctrl = ALU_LOAD;
						a_load = 1'b0;
						pc_inc = 1'b0;
						z_load = 1'b0;
					end
                .
                .
                .

                // add more instructions

                .
                .
                .

				endcase
				EX2:  
                .
                .
                .

                // add more instructions

                .
                .
                .

			endcase
		end
endmodule