MAR, OUT, ACCA, and INST, are all 8-bit registers with synchronous parallel load. These registers all have a clock input, an 8-bit data input, and an active low load/enable input, as well as an 8-bit output.
For example, when MAR_L (Memory Addressing Register Load) is VCC the MAR register is not enabled. When MAR_L goes low the MAR register is enabled and on the next clock pulse the 8-bit data on the input line is loaded into the MAR register.
The PC is an 8-bit register with synchronous parallel load capability, synchronous count, and an asynchronous reset. The PC has a clock input, an 8-bit data input, and 3 additional inputs: PC_L, PC_I, and RESET. These three inputs are all active low. PC_L loads the program counter, PC_I increments the program counter by 1, and RESET resets the program counter to 0.
Implement these registers (synchronous load and synchronous load/count) as Altera functions. Include each one in a higher-level design file. Use a DIP switch for the input data, and switches on the evaluation board for LOAD, INC, and CLOCK. Verify that the load function works correctly for the parallel load register, and that the load and increment functions work correctly for the load/increment register.