`include "constants.v" module mem_block ( input [7:0] data_in, input [7:0] input_port, input [7:0] address, input clk, input we, input reset, output [7:0] data_out, output reg [7:0] output_port ); reg [7:0] mem [0:127]; assign data_out = (address == 8'h00) ? output_port : (address == 8'h01) ? input_port : (address[7] == 1'b1) ? mem[address[6:0]]: 8'hxx; always @ (posedge clk or negedge reset) if (~reset) begin mem[7'h00] <= 8'h00; // Address 0x80 mem[7'h01] <= 8'h00; // Address 0x81 mem[7'h02] <= 8'h00; // Address 0x82 mem[7'h03] <= 8'h00; // Address 0x83 mem[7'h04] <= 8'h00; // Address 0x84 mem[7'h05] <= 8'h00; // Address 0x85 mem[7'h06] <= 8'h00; // Address 0x86 mem[7'h07] <= 8'h00; // Address 0x87 mem[7'h08] <= 8'h00; // Address 0x88 mem[7'h09] <= 8'h00; // Address 0x89 mem[7'h0a] <= 8'h00; // Address 0x8a mem[7'h0b] <= 8'h00; // Address 0x8b mem[7'h0c] <= 8'h00; // Address 0x8c mem[7'h0d] <= 8'h00; // Address 0x8d mem[7'h0e] <= 8'h00; // Address 0x8e mem[7'h0f] <= 8'h00; // Address 0x8f mem[7'h10] <= 8'h00; // Address 0x90 mem[7'h11] <= 8'h00; // Address 0x91 mem[7'h12] <= 8'h00; // Address 0x92 mem[7'h13] <= 8'h00; // Address 0x93 mem[7'h14] <= 8'h00; // Address 0x94 mem[7'h15] <= 8'h00; // Address 0x95 mem[7'h16] <= 8'h00; // Address 0x96 mem[7'h17] <= 8'h00; // Address 0x97 mem[7'h18] <= 8'h00; // Address 0x98 mem[7'h19] <= 8'h00; // Address 0x99 mem[7'h1a] <= 8'h00; // Address 0x9a mem[7'h1b] <= 8'h00; // Address 0x9b mem[7'h1c] <= 8'h00; // Address 0x9c mem[7'h1d] <= 8'h00; // Address 0x9d mem[7'h1e] <= 8'h00; // Address 0x9e mem[7'h1f] <= 8'h00; // Address 0x9f mem[7'h20] <= 8'h00; // Address 0xa0 mem[7'h21] <= 8'h00; // Address 0xa1 mem[7'h22] <= 8'h00; // Address 0xa2 mem[7'h23] <= 8'h00; // Address 0xa3 mem[7'h24] <= 8'h00; // Address 0xa4 mem[7'h25] <= 8'h00; // Address 0xa5 mem[7'h26] <= 8'h00; // Address 0xa6 mem[7'h27] <= 8'h00; // Address 0xa7 mem[7'h28] <= 8'h00; // Address 0xa8 mem[7'h29] <= 8'h00; // Address 0xa9 mem[7'h2a] <= 8'h00; // Address 0xaa mem[7'h2b] <= 8'h00; // Address 0xab mem[7'h2c] <= 8'h00; // Address 0xac mem[7'h2d] <= 8'h00; // Address 0xad mem[7'h2e] <= 8'h00; // Address 0xae mem[7'h2f] <= 8'h00; // Address 0xaf mem[7'h30] <= 8'h00; // Address 0xb0 mem[7'h31] <= 8'h00; // Address 0xb1 mem[7'h32] <= 8'h00; // Address 0xb2 mem[7'h33] <= 8'h00; // Address 0xb3 mem[7'h34] <= 8'h00; // Address 0xb4 mem[7'h35] <= 8'h00; // Address 0xb5 mem[7'h36] <= 8'h00; // Address 0xb6 mem[7'h37] <= 8'h00; // Address 0xb7 mem[7'h38] <= 8'h00; // Address 0xb8 mem[7'h39] <= 8'h00; // Address 0xb9 mem[7'h3a] <= 8'h00; // Address 0xba mem[7'h3b] <= 8'h00; // Address 0xbb mem[7'h3c] <= 8'h00; // Address 0xbc mem[7'h3d] <= 8'h00; // Address 0xbd mem[7'h3e] <= 8'h00; // Address 0xbe mem[7'h3f] <= 8'h00; // Address 0xbf mem[7'h40] <= 8'h00; // Address 0xc0 mem[7'h41] <= 8'h00; // Address 0xc1 mem[7'h42] <= 8'h00; // Address 0xc2 mem[7'h43] <= 8'h00; // Address 0xc3 mem[7'h44] <= 8'h00; // Address 0xc4 mem[7'h45] <= 8'h00; // Address 0xc5 mem[7'h46] <= 8'h00; // Address 0xc6 mem[7'h47] <= 8'h00; // Address 0xc7 mem[7'h48] <= 8'h00; // Address 0xc8 mem[7'h49] <= 8'h00; // Address 0xc9 mem[7'h4a] <= 8'h00; // Address 0xca mem[7'h4b] <= 8'h00; // Address 0xcb mem[7'h4c] <= 8'h00; // Address 0xcc mem[7'h4d] <= 8'h00; // Address 0xcd mem[7'h4e] <= 8'h00; // Address 0xce mem[7'h4f] <= 8'h00; // Address 0xcf mem[7'h50] <= 8'h00; // Address 0xd0 mem[7'h51] <= 8'h00; // Address 0xd1 mem[7'h52] <= 8'h00; // Address 0xd2 mem[7'h53] <= 8'h00; // Address 0xd3 mem[7'h54] <= 8'h00; // Address 0xd4 mem[7'h55] <= 8'h00; // Address 0xd5 mem[7'h56] <= 8'h00; // Address 0xd6 mem[7'h57] <= 8'h00; // Address 0xd7 mem[7'h58] <= 8'h00; // Address 0xd8 mem[7'h59] <= 8'h00; // Address 0xd9 mem[7'h5a] <= 8'h00; // Address 0xda mem[7'h5b] <= 8'h00; // Address 0xdb mem[7'h5c] <= 8'h00; // Address 0xdc mem[7'h5d] <= 8'h00; // Address 0xdd mem[7'h5e] <= 8'h00; // Address 0xde mem[7'h5f] <= 8'h00; // Address 0xdf mem[7'h60] <= 8'h00; // Address 0xe0 mem[7'h61] <= 8'h00; // Address 0xe1 mem[7'h62] <= 8'h00; // Address 0xe2 mem[7'h63] <= 8'h00; // Address 0xe3 mem[7'h64] <= 8'h00; // Address 0xe4 mem[7'h65] <= 8'h00; // Address 0xe5 mem[7'h66] <= 8'h00; // Address 0xe6 mem[7'h67] <= 8'h00; // Address 0xe7 mem[7'h68] <= 8'h00; // Address 0xe8 mem[7'h69] <= 8'h00; // Address 0xe9 mem[7'h6a] <= 8'h00; // Address 0xea mem[7'h6b] <= 8'h00; // Address 0xeb mem[7'h6c] <= 8'h00; // Address 0xec mem[7'h6d] <= 8'h00; // Address 0xed mem[7'h6e] <= 8'h00; // Address 0xee mem[7'h6f] <= 8'h00; // Address 0xef mem[7'h70] <= 8'h00; // Address 0xf0 mem[7'h71] <= 8'h00; // Address 0xf1 mem[7'h72] <= 8'h00; // Address 0xf2 mem[7'h73] <= 8'h00; // Address 0xf3 mem[7'h74] <= 8'h00; // Address 0xf4 mem[7'h75] <= 8'h00; // Address 0xf5 mem[7'h76] <= 8'h00; // Address 0xf6 mem[7'h77] <= 8'h00; // Address 0xf7 mem[7'h78] <= 8'h00; // Address 0xf8 mem[7'h79] <= 8'h00; // Address 0xf9 mem[7'h7a] <= 8'h00; // Address 0xfa mem[7'h7b] <= 8'h00; // Address 0xfb mem[7'h7c] <= 8'h00; // Address 0xfc mem[7'h7d] <= 8'h00; // Address 0xfd mem[7'h7e] <= 8'h00; // Address 0xfe mem[7'h7f] <= 8'h00; // Address 0xff RESET VECTOR end else begin if ((address == 8'h00) && (~we)) output_port <= data_in; if ((address[7]) && (~we)) mem[address[6:0]] <= data_in; end endmodule