module mem_block ( input [7:0] data_in, input [7:0] input_port, input [7:0] address, input clk, input we, input reset, output [7:0] data_out, output reg [7:0] output_port ); reg [7:0] mem [0:127]; assign data_out = (address == 8'h00) ? output_port : (address == 8'h01) ? input_port : (address[7] == 1'b1) ? mem[address[6:0]]: 8'hxx; always @ (posedge clk or negedge reset) if (~reset) begin `include "mem_init.v" end else begin if ((address == 8'h00) && (~we)) output_port <= data_in; if ((address[7]) && (~we)) mem[address[6:0]] <= data_in; end endmodule