EE 101

Lab Exercise 7: Introduction to Logic Gates

The pinout schemes for the logic gates you will be using in this exercise are given in Figure 1. Note that for all of these chips, Vcc = 5V (pin 14) and GND = 0V (pin 7). Also, note that the pins that are inputs on some chips are not necessarily the inputs on other chips!

 

 

Figure 1

1. Fill out the truth tables for each gate shown above. Under "V", indicate the voltage of the output, as indicated by a voltage meter. Under F, record the logic level ("1" or "0") as indicated by the logic probe.

 

74HC04 (NOT) 74HC08 (AND) 74HC32 (OR) 74HC00 (NAND) 74HC02 (NOR)
A V F A B V F A B V F A B V F A B V F
0 0 0 0 0 0 0 0 0
1 0 1 0 1 0 1 0 1
1 0 1 0 1 0 1 0
1 1 1 1 1 1 1 1

 

2. The following exercises deal with the schematic in Figure 2.

Figure 2

 

a. From the schematic, derive the Boolean equation for the output, F.

b. Write out a truth table based on the equation you derived in part 2a.

c. Construct the circuit in Figure 2. (Remember to hookup Vcc (+5V) and ground.) Using a logic probe, observe the values of the output for every possible combination of input. Construct a truth table with your results.

d. The truth table you derived in part 2b should have agreed with the truth table you observed in part 2c. If your two truth tables did not agree, list any problems you found and what you did to correct them.

3. The following exercises deal with the schematic in Figure 3.

 

Figure 3

 

 

a. From the schematic, derive the Boolean equation for the output, F.

b. Write out a truth table based on the equation you derived in part 3a.

c. Construct the circuit in Figure 3. (Remember to hookup Vcc (+5V) and ground.) Using a logic probe, observe the values of the output for every possible combination of input. Construct a truth table with your results.

d. The truth table you derived in part 3b should have agreed with the truth table you observed in part 3c. If your two truth tables did not agree, list any problems you found and what you did to correct them.

Questions:

1. Is it possible to create a NAND gate by attaching another gate to the output of an AND gate? If so, draw a schematic showing how it would be done.

2. Draw a schematic for this Boolean equation: F = A’BC + ABC’ + ABC. Include chip reference numbers (UX), pin numbers, and gate identifiers (74HCXX) along with the inputs and output.

3. Draw a truth table for the equation in question 2.