Your assignment in this lab exercise is to use a programmable logic device (PLD) to implement a combinational logic circuit. The circuit you will program into the Altera EPM7032 EPLD is a simple majority circuit. For this lab, the AHDL (Altera Hardware Description Language) file that you would normally be responsible for writing has been provided for you below. The purpose of this exercise is merely to familiarize you with the Altera PLD programming software.

 A sample AHDL program, below, implements the majority circuit. The truth table for this circuit is shown in Figure 2. The canonical sum of products expression for the majority circuit is F = !ABC + A!BC + AB!C + ABC. Note that we did not reduce the equation before writing the Altera text design file below. The Max+plus II software does this automatically.
 
 

A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

1. Login to a PC (Windows NT network).  Load up the Altera (MaxPlus II) software.

 

 
 
 

2. Under the File menu, select New. A small window will appear. Click on Text Editor File and OK. A window will appear. Before doing anything else, go to the File menu and choose Save As. Select the U: drive and, in the File Name field, type in majority.tdf and click on OK

 

 
 
 

3. From the File menu choose Project and choose Name. Enter "majority" in the Project Name field, or select majority with the mouse and click on OK. Your path (u:\) and project name should appear on he bar at the top of the screen after a short wait.

 

 
 
 

4. Type the program as given in Figure 1 in the majority.tdf window. It would be wise to save your program (File menu, Save) after you complete every few lines. This way, if your computer or the network "crashes", you will not have to retype all of your work.

 

 

 After you have finished typing in the program, save it one more time. Then, go to the Max+plus II menu and choose Compiler. Do not hit the Start button yet.

 Before starting the compilation, you will specify the device type you want to use. Lots of PLDs are supported by the Max+plus II software, and there is a built-in feature that lets Altera pick the best chip for you. The PLD we are using in this lab is the EPM7032LC44.

 We will make sure that the proper device and package are chosen by first going to the Assign menu and selecting Device. First, uncheck the box that reads Show Only Fastest Speed Grades. You should see two fields, one for Device family and the other for specific Devices. In the Device Family Field, select MAX7000 (if it is not already selected). In the devices field, select EPM7032LC44-15. Hit OK.

Now click the Start button on the compiler window. If there is problem with the .tdf file you created, you will find out now. If the compilation process stops and reports errors, fix these, re-save your program, and resume compiling (hit the Start button again). Ask for assistance if you have trouble fixing your errors and compiling. After the program compiles with no errors, hit OK. After compilation, several new files have been added to your directory. They are all called majority, but their extensions vary: .cnf, .fin, .fit, .hif, .ini, .mmf, .pof, .prb, .rpt, .snf, and .sym.

5. Take a look at your .rpt file. (File, Open majority.rpt, or just click the rpt icon in the compiler window). Scroll down to find the picture of the chip. Note the pinout, and which pins are connected to what, and which are deliberately not connected. Find the area where the device, turbo, and security options are listed (right above the pinout). Add your name around this area.

 

 

By highlighting the area with your mouse, select your name, the picture of the PLD, and the pinout information which follows it. Print out your highlighted portion. (File ~ Print ~ 1 copy ~ Selected Area). Go to the printer and wait for your printout. You will use this picture of the chip to wire up your circuit.

6. Simulate your program. Altera has a feature that allows you to simulate your program before you actually take the time to build your circuit.
1. From the File menu, select New. Specify a waveform file with an extension of .scf. A simulation file window will appear.

 

 
 
 

2. In the simulator file window, go to the Node menu and select Enter Nodes from SNF. Boxes for the input and output signals should already be checked. Click on the List button. The A, B, and C inputs and the F output will be listed (and highlighted) in the Available Nodes & Groups field. Click on the right arrow to send these signals to the Selected Nodes & Groups field. Click on the OK button to close the signal selection window. Signals A, B, C, and F should show up in your simulator window.

 

 
 
 

3. Click the File menu and select End Time. Enter a total simulation time of 800ns. Go to the Options menu and select Grid Size. Enter a grid size of 100ns

 

 
 
 

4. Click on the tab next to the C input signal. The entire waveform for C should become highlighted. Go to the Edit menu and select Overwrite and then Count Value. Click on OK. The C signal should have become a periodic TTL waveform. (If needed, adjust the zoom controls so that you can see 4 high parts and 4 low parts for the C signal.) In the same way, highlight the B signal, go to the Edit menu and Select Overwrite. This time, enter a value of 2 in the Multiplied By box and choose OK. Finally, highlight the A signal and overwrite it as you did the others, changing the Multiplied By box to 4. Note that signals A, B, and C count from 000₂ to 111₂.

 

 
 
 

5. Save your file as majority.scf. Under the Max+plus II menu choose Simulator and Start. The F signal should be generated. Draw a truth table showing the results of your simulation. If your truth table does not agree with the one from Figure 1, check the program you wrote for obvious problems.
7. Program your chip. The Altera programmer is located in the Southwest corner of the lab. Since the programmer PC is networked with the rest of the lab, you can access your files from there. When you are ready to program your chip, let a lab assistant know so he or she can guide you through the process.

 

 
 
 

8. Take your chip back to your workstation and install it in the PLCC adapter board. Note that certain pins are always going to be tied to Vcc and GND. For the EPM7032, pins 3, 15, 23 and 35 are always tied to Vcc, and pins 10, 22, 30 and 42 are always tied to ground. We have designed the adapter board to join these Vcc and ground pins together. All you have to do is to connect a single wire from the VCC port on the adapter to +5 volts on the protoboard, and another wire from GND on the adapter to ground on the protoboard. Note (from the printout of your chip) that there are possibly other grounds and Vcc’s that you will still need to hook up. These pin assignments will vary from project to project.

 

 

Take care that your chip has the proper orientation, and let a lab assistant witness you plugging the chip into its socket. Make sure all GND and Vcc wires are hooked up properly to the device.

Wire up your counter (74HC4040) as described in the pre-lab lecture and your programmed Altera chip. The outputs of the counter chip will be hooked up as inputs to the Altera chip. The "clock" input of the counter chip will be driven by the clock on the protoboard. The clock will cycle through all possible inputs for your Altera chip, saving you from having to wire each combination of the inputs by hand for testing.
 
 

9. Once you are convinced your circuit is hooked up properly, hook the logic analyzer up to your circuit. You need to hook up 5 lines - three to the outputs of the counter chip (inputs to the Altera), one to the output of the Altera chip, and one as a common ground.

 

 

 Note: When working with digital circuits, it is extremely important to establish a common ground between all parts of the circuit and any instruments acting on the circuit. Otherwise, the circuit simply may not work. On the logic analyzer pod, locate a ground lead (labeled GND) and plug this into a GROUND on the protoboard. This estables a common ground between your circuit and the logic analyzer.

 You will now hook the logic analyzer up to the inputs and output of your circuit. It is an unfortunate, but somewhat unavoidable occurrence that the logic analyzer lines tend to break. Whenever this happens, we try to put a tag on the logic analyzer pod indicating which lines do not presently work. Look at the logic analyzer pod for any such note. The following instructions assume your pod is fully functional. If you have a pod where any of the first three lines are not working, do not use these lines, but simply use the next available ones.
 
 

1. Place another pin header alongside the one where A, B, and C tie into your circuit so that you will have another set of nodes that tie to those inputs.

 

 
 
 

2. From the logic analyzer pod, attach line 1 to signal A on the pin header. Likewise, attach lines 2 and 3 to signals B and C, respectively. Having the three input stimuli attached to the logic analyzer will enable you to monitor your A, B, and C inputs. Next, attach line 4 from the logic analyzer pod to a pin header that comes into contact with the output ("F") of your circuit.

 

 
 
 

3. Call one of the lab TA’s over to look over your wiring.

 

 
 
 

10. Login to a PC (Windows NT network) and load the logic analyzer software (PA485 on the taskbar, under the Applications  menu).
1. Double click on the Field Editor icon. A channel number versus signal name chart appears. Wherever there is an asterisk, this means that that particular channel number is mapped to that signal name. For instance, when you first invoked the field editor, "control" was mapped to channels 41 through 48, "databus" was mapped to channels 25 through 40, and "addrbus" was mapped to channels 1 through 24. At this time, click the mouse on each asterisk to make them disappear (and thus destroy the default channel to signal name mapping scheme).

 

 
 
 

2. Go back to the vertical column where the default signal names are (control, databus, and addrbus). Go to the first field ("control") and activate it with the mouse. Press the delete key to remove "control" and then type an "A" in its place. Similarly, do this to the next three fields and type "B", "C", and "F" in each one, respectively.

 

 
 
 

3. Across from where you entered the "A" signal name, click the mouse under channel 1 so an asterisk appears. In the same way, across from signal B, click under channel 2. For signal C map channel 3, and for the output F, map channel 4.

 

 
 
 

4. Under the Edit menu, select clock setup. Change the clock mode (sampling rate) to 100 KHz.

 

 
 
 

5. Click on the Internal Trigger Patterns icon to activate a trigger point. You should see a column for every signal you have defined. Under all your inputs, replace the "x" with a "0" in the pattrn01 row. Leave the output column, F, as an "x". The logic analyzer is now configured to begin data collection when it senses A, B, and C to be zeros.

 

 
 
 

6. Under the File menu, select Save and then Setup Conditions. Save the setup conditions you just configured in a file with a .set extension (for example, lab9.set or 3bit.set).

 

 
 
 

7. Turn the protoboard on. Go back to the logic analyzer window and click the mouse on the Go button. If everything is working, the logic analyzer should trigger (you should hear a beep when the logic analyzer triggers). If your logic analyzer does not trigger, call for assistance.

 

 

 If the logic analyzer is working properly, a window with waveforms for the input and output signals may appear. Or, you may have to maximize the waveform display from icon form.

 Once the waveforms are visible (and each signal is toggling properly -- no flat liners!), verify the output for each state with the truth table in Figure 2.

 Zoom in or out so that you can read the waveforms easily. Print out your waveform data and include this in your lab book.

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