EE 231
Prelab 8: Introduction to Clocked Sequential Circuits

1. Modulo three counter using D flip-flops
   1. Derive the excitation equations for a modulo three counter using D flip-flops.
   2. Draw a schematic for a divide by three counter using 74HC74 flip flops. Don't forget the set and reset inputs. Design the counter using a .gdf file and print the simulation (i.e. scf) waveform. Be sure to include the clock, both D inputs, and Q outputs in your waveform.
      
2. Modulo four up down counter using a programmable logic device.

   The EMP7064LC44-15 contains internal D flip flops and it can be used to construct sequential state machines.

   The AHDL language can work directly with state diagram specifications. Three example programs to do the divide by three counter are given in Lab 8. Your program for the four up down counter, can be patterned after any of the three. The third has an enable that turns the counter to wait or count. An enable could have been included in the table of the first two.

Write an AHDL program to do a divide by four up-down counter. In other words, generate the sequence

.... 00, 01, 10, 11, 00, 01, 10, 11 ...

if the input "UP'' is active (i.e. UP=1), and the sequence

..... 11, 10, 01, 00, 11, 10, 01, 00, ...

if the input "UP'' is not active(i.e. UP=0).