%-----------------------------------------------------------* * A basic FSM that outputs a single clock cycle wide pulse * * (enter_out) for each pulse seen on the input (enter_in) * * Author: Dr. Stephen Bruder * * Date: 10/25/00 * *-----------------------------------------------------------*% SUBDESIGN sync_switch ( enter_in, clock, rst : INPUT; enter_out : OUTPUT; ) VARIABLE ss: MACHINE WITH STATES (S0, S1, S2); BEGIN ss.clk = !clock; % This machine is clocked on the falling edge % ss.reset = rst; % Asynchronous active high reset % TABLE % Current Input Next Output % % State State % ss, enter_in => ss, enter_out; S0, 0 => S0, 0; S0, 1 => S1, 0; S1, X => S2, 1; S2, 0 => S0, 0; S2, 1 => S2, 0; END TABLE; END;