**Lecture Outline for Spring 2010**

Wednesday 8/25

**Introduction to Digital Electronics**- Mano, Sections 1.1 through 1.4
- Course Overview
- Binary and hexadecimal numbers
- Conversion between decimal and hexadecimal numbers
- Binary and hexadecimal addition and subtraction

Friday 8/27

**Binary and Hexadecimal Numbers**- Mano, Sections 1.5 through 1.7
- One's and two' complements of binary numbers
- Taking one's and two's complements of a binary number using hexadecimal numbers
- Using two's complements to subtract binary and hex numbers
- Unsigned binary numbers
- Two's complement representation of signed binary numbers

Monday 8/30

**Binary and Hexadecimal Numbers**- Mano, Sections 1.5 through 1.7
- More on unsigned and 2's compliment signed representations of binary numbers
- Addition and subtraction of signed and unsigned numbers
- How to tell is answer in fixed word size is correct
- Binary codes

Wednesday 9/1

**Register Transfer Logic and Basic Logic Gates****Introduction to Boolean Algebra**- Mano, Sections 1.8 through 1.9
- Mano, Sections 2.1 through 2.4
- What is a register?
- Intro to register transfer logic
- Basic logic gates: AND, OR, NOT
- Intro to Boolean Algebra
- Boolean postulates and theorems
- Proof of Boolean postulates and theorems using truth tables
- Complement of a function using DeMorgan's theorem

Friday 9/3

**Canonical and Standard Forms**- Mano, Sections 2.6
- Definition of minterm and maxterm
- Expressing a Boolean function in canonical forms: Sum of minterms or product of maxterms
- Expressing a Boolean function in standard forms: Sum of products or product of sums
- Generating a truth table from a Boolean expression

Wednesday 9/8

**Logic Operations, Digital Gates, Integrated Circuits**- Mano, Sections 2.7 through 2.9
- More on minterms, maxterms, standard and canonical forms
- 16 logic operations on two inputs
- Logic gates for two inputs - AND, NAND, OR, NOR, XOR, XNOR

Friday 9/10

**Integrated Circuits**- Mano, Sections 2.8 through 2.9
**Minimization, Karnaugh Maps**- Mano, Sections 3,1 through 3.3
- Brief discussion of digital IC families
- Introduction to HDL (Hardware Description Language)
- Karnaugh Maps

Monday 9/12

**More on Karnaugh Maps**- Mano, Sections 3.3 through 3.4

Wednesday 9/14

**Sum of Products and Product of Sums**- Mano, Section 3.5

Friday 9/16

**Implicants, Prime Implicants, Don't Cares**- Mano, Section 3.6

Monday 9/20

**Implementation with NAND, NOR, XOR gates**- Mano, Section 3.7 through 3.9

Wednesday 9/22

**Exam 1 (Tentative)**

Friday 9/24

**Introdution to Combinational Logic**- Mano, Sections 4.1 through 4.3

Monday 9/27

**Full Adder**- Mano, Sections 4.4 through 4.5

Wednesday 9/29

**Ripple Adder, Carry Lookahead, Comparator, Decoder**- Mano, Sections 4.6 through 4.8

Friday 10/1

**Digital logic using decoders, encoders and multiplexers; tri-state logic**- Mano, Sections Sections 4.9 through 4.11

Monday 10/4

**Design of an ALU (Arithmetic Logic Unit)**

Wednesday 10/6

**Introduction to Sequential Logic**- Mano, Sections 5.1 through 5.2

Friday 10/8

**RS Latch, D Flip-Flop, State Diagrams**- Mano, Sections 5.3 through 5.4

Monday 10/11

**More on State Diagrams**- Mano, Section 5.5

Wednesday 10/13

**Exam 2 (Tentative)**

Friday 10/15

**Design of Synchronous Sequential Circuits; Moore and Mealy Machines**- Mano, Section 5.6

Monday 10/18

**Design of Synchronous Sequential Circuits using State Diagrams**- Mano, Section 5.7

Wednesday 10/20

**Design Example**- Mano, Section 5.8

Monday 10/25

**Examples of Synchronous Sequential Cirucuits - Registers and Counters**- Mano, Section 6.1 through 6.2

Wednesday 10/27

**Registers and Counters in Verilog**

Friday 10/29

**More on Registers and Counters in Verilog**

Monday 11/1

**Registers: Parallel Load and Shift**- Mano, Sections 6.2 through 6.3

Wednesday 11/3

**Johnson Counter, Gray Code Counter**- Mano, Sections 6.4 through 6.5

Friday 11/5

**Memory: RAM (Random Access Memory)**- Mano, Sections 7.1 through 7.2

Monday 11/8

**Memory Decoding; Error Detection and Correction**- Mano, Sections 7.3 through 7.4

Wednesday 11/10

**Memory: ROM (Read-Only Memory)**- Mano, Sections 7.5

Friday 11/12

**Exam 3**

Monday 11/15

**Programmable Logic**- Mano, Sections 7.6 through 7.7

Wednesday 11/17

**Register Transfer Logic**- Mano, Sections 8.1 through 8.3

Friday 11/19

**ASM (Algorithmic State Machine) Diagrams**- Mano, Sections 8.4 through 8.5

Monday 11/22

**Design Example using ASM**- Mano, Sections 8.6

Wednesday 11/24

**More Desing Examples: Sequential Binary Multiplier**- Mano, Sections 8.7 through 8.9

Monday 11/29

**More on Verilog HDL**- Mano, Section 8.3

Wednesday 12/1

**Discussion of Final Lab - Verilog Microprocessor Design**

Friday 12/3

**Discussion of Final Lab - Verilog Microprocessor Design**

Monday 12/6

**Exam 4 (Tentative)**

Wednesday 12/8

**TBD**

Friday 12/10

**TBD**