## EE 231

Lecture Outline for Spring 2010

1. Wednesday 8/25

• Introduction to Digital Electronics
• Mano, Sections 1.1 through 1.4
• Course Overview
• Conversion between decimal and hexadecimal numbers

2. Friday 8/27

• Mano, Sections 1.5 through 1.7
• One's and two' complements of binary numbers
• Taking one's and two's complements of a binary number using hexadecimal numbers
• Using two's complements to subtract binary and hex numbers
• Unsigned binary numbers
• Two's complement representation of signed binary numbers

3. Monday 8/30

• Mano, Sections 1.5 through 1.7
• More on unsigned and 2's compliment signed representations of binary numbers
• Addition and subtraction of signed and unsigned numbers
• How to tell is answer in fixed word size is correct
• Binary codes

4. Wednesday 9/1

• Register Transfer Logic and Basic Logic Gates
• Introduction to Boolean Algebra
• Mano, Sections 1.8 through 1.9
• Mano, Sections 2.1 through 2.4
• What is a register?
• Intro to register transfer logic
• Basic logic gates: AND, OR, NOT
• Intro to Boolean Algebra
• Boolean postulates and theorems
• Proof of Boolean postulates and theorems using truth tables
• Complement of a function using DeMorgan's theorem
5. Friday 9/3

• Canonical and Standard Forms
• Mano, Sections 2.6
• Definition of minterm and maxterm
• Expressing a Boolean function in canonical forms: Sum of minterms or product of maxterms
• Expressing a Boolean function in standard forms: Sum of products or product of sums
• Generating a truth table from a Boolean expression
6. Wednesday 9/8

• Logic Operations, Digital Gates, Integrated Circuits
• Mano, Sections 2.7 through 2.9
• More on minterms, maxterms, standard and canonical forms
• 16 logic operations on two inputs
• Logic gates for two inputs - AND, NAND, OR, NOR, XOR, XNOR
7. Friday 9/10

• Integrated Circuits
• Mano, Sections 2.8 through 2.9
• Minimization, Karnaugh Maps
• Mano, Sections 3,1 through 3.3
• Brief discussion of digital IC families
• Introduction to HDL (Hardware Description Language)
• Karnaugh Maps
8. Monday 9/12

• More on Karnaugh Maps
• Mano, Sections 3.3 through 3.4
9. Wednesday 9/14

• Sum of Products and Product of Sums
• Mano, Section 3.5
10. Friday 9/16

• Implicants, Prime Implicants, Don't Cares
• Mano, Section 3.6
11. Monday 9/20

• Implementation with NAND, NOR, XOR gates
• Mano, Section 3.7 through 3.9
12. Wednesday 9/22

• Exam 1 (Tentative)
13. Friday 9/24

• Introdution to Combinational Logic
• Mano, Sections 4.1 through 4.3
14. Monday 9/27

• Mano, Sections 4.4 through 4.5
15. Wednesday 9/29

• Mano, Sections 4.6 through 4.8
16. Friday 10/1

• Digital logic using decoders, encoders and multiplexers; tri-state logic
• Mano, Sections Sections 4.9 through 4.11
17. Monday 10/4

• Design of an ALU (Arithmetic Logic Unit)
18. Wednesday 10/6

• Introduction to Sequential Logic
• Mano, Sections 5.1 through 5.2
19. Friday 10/8

• RS Latch, D Flip-Flop, State Diagrams
• Mano, Sections 5.3 through 5.4
20. Monday 10/11

• More on State Diagrams
• Mano, Section 5.5
21. Wednesday 10/13

• Exam 2 (Tentative)
22. Friday 10/15

• Design of Synchronous Sequential Circuits; Moore and Mealy Machines
• Mano, Section 5.6
23. Monday 10/18

• Design of Synchronous Sequential Circuits using State Diagrams
• Mano, Section 5.7
24. Wednesday 10/20

• Design Example
• Mano, Section 5.8
25. Monday 10/25

• Examples of Synchronous Sequential Cirucuits - Registers and Counters
• Mano, Section 6.1 through 6.2
26. Wednesday 10/27

• Registers and Counters in Verilog
27. Friday 10/29

• More on Registers and Counters in Verilog
28. Monday 11/1

• Registers: Parallel Load and Shift
• Mano, Sections 6.2 through 6.3
29. Wednesday 11/3

• Johnson Counter, Gray Code Counter
• Mano, Sections 6.4 through 6.5
30. Friday 11/5

• Memory: RAM (Random Access Memory)
• Mano, Sections 7.1 through 7.2
31. Monday 11/8

• Memory Decoding; Error Detection and Correction
• Mano, Sections 7.3 through 7.4
32. Wednesday 11/10

• Mano, Sections 7.5
33. Friday 11/12

• Exam 3
34. Monday 11/15

• Programmable Logic
• Mano, Sections 7.6 through 7.7
35. Wednesday 11/17

• Register Transfer Logic
• Mano, Sections 8.1 through 8.3
36. Friday 11/19

• ASM (Algorithmic State Machine) Diagrams
• Mano, Sections 8.4 through 8.5
37. Monday 11/22

• Design Example using ASM
• Mano, Sections 8.6
38. Wednesday 11/24

• More Desing Examples: Sequential Binary Multiplier
• Mano, Sections 8.7 through 8.9
39. Monday 11/29

• More on Verilog HDL
• Mano, Section 8.3
40. Wednesday 12/1

• Discussion of Final Lab - Verilog Microprocessor Design
41. Friday 12/3

• Discussion of Final Lab - Verilog Microprocessor Design
42. Monday 12/6

• Exam 4 (Tentative)
43. Wednesday 12/8

• TBD
44. Friday 12/10

• TBD
Note: Lecture figures may be presented in Adobe Acrobat format. You need to open those using the Adobe Acrobat Reader program. This is a free program available from Adobe:

Bill Rison, <rison@ee.nmt.edu >