/* IO DEFINITIONS FOR MCS912DP256 * Copyright (c) 2000 by COSMIC Software */ #ifndef _BASE #define _BASE 0 #endif #define _IO(x) @(_BASE)+(x) #if _BASE == 0 #define _PORT @dir #else #define _PORT #endif #define uint unsigned int /* MEBI Module */ _PORT volatile char PORTA _IO(0x00); /* port A */ _PORT volatile char PORTB _IO(0x01); /* port B */ _PORT volatile char DDRA _IO(0x02); /* data direction port A */ _PORT volatile char DDRB _IO(0x03); /* data direction port B */ _PORT volatile char PORTE _IO(0x08); /* port E */ _PORT volatile char DDRE _IO(0x09); /* data direction port E */ _PORT volatile char PEAR _IO(0x0a); /* port E assignment register */ _PORT volatile char MODE _IO(0x0b); /* mode register */ _PORT volatile char PUCR _IO(0x0c); /* pull-up control register */ _PORT volatile char RDRIV _IO(0x0d); /* reduced drive of I/O lines */ _PORT volatile char EBICTL _IO(0x0e); /* external bus interface control */ /* MMC Module */ _PORT volatile char INITRM _IO(0x10); /* RAM mapping register */ _PORT volatile char INITRG _IO(0x11); /* IO mapping register */ _PORT volatile char INITEE _IO(0x12); /* EEPROM mapping register */ _PORT volatile char MISC _IO(0x13); /* mapping control register */ _PORT volatile char MTST0 _IO(0x14); /* mapping test register 0 */ /* INT Module */ _PORT volatile char ITCR _IO(0x15); /* interrupt test control reg. */ _PORT volatile char ITEST _IO(0x16); /* interrupt test register */ /* MMC Module */ _PORT volatile char MTST1 _IO(0x17); /* mapping test register 1 */ _PORT volatile uint PARTID _IO(0x1a); /* part ID register */ _PORT volatile char MEMSIZ0 _IO(0x1c); /* memory size register 0 */ _PORT volatile char MEMSIZ1 _IO(0x1d); /* memory size register 1 */ /* INT Module */ _PORT volatile char INTCR _IO(0x1e); /* interrupt control */ _PORT volatile char HPRIO _IO(0x1f); /* highest priority */ /* BKP Module */ _PORT volatile char BKPCT0 _IO(0x28); /* Breakpoint Control 0 */ _PORT volatile char BKPCT1 _IO(0x29); /* Breakpoint Control 1 */ _PORT volatile char BKP0X _IO(0x2a); /* Breakpoint 0 address upper */ _PORT volatile uint BKP0 _IO(0x2b); /* Breakpoint 0 address */ _PORT volatile char BKP1X _IO(0x2d); /* Breakpoint 1 address upper */ _PORT volatile uint BKP1 _IO(0x2e); /* Breakpoint 1 address */ /* MEBI Module */ _PORT volatile char PPAGE _IO(0x30); /* program page register */ _PORT volatile char PORTK _IO(0x32); /* port K data register */ _PORT volatile char DDRK _IO(0x33); /* port K data direction */ /* CRG Module */ _PORT volatile char SYNR _IO(0x34); /* synthesizer register */ _PORT volatile char REFDV _IO(0x35); /* reference divider register */ _PORT volatile char CTFLG _IO(0x36); /* clock test flag register */ _PORT volatile char CRGFLG _IO(0x37); /* clock generator flag register */ _PORT volatile char CRGINT _IO(0x38); /* clock interrupt enable */ _PORT volatile char CLKSEL _IO(0x39); /* clock select register */ _PORT volatile char PLLCTL _IO(0x3a); /* PLL control register */ _PORT volatile char RTICTL _IO(0x3b); /* clock real time control reg. */ _PORT volatile char COPCTL _IO(0x3c); /* COP control register */ _PORT volatile char FORBYP _IO(0x3d); /* clock force and bypass register */ _PORT volatile char CTCTL _IO(0x3e); /* clock test control register */ _PORT volatile char ARMCOP _IO(0x3f); /* COP arm/reset register */ /* Enhanced Capture Timer Module */ _PORT volatile char TIOS _IO(0x40); /* timer select register */ _PORT volatile char TCFORC _IO(0x41); /* compare force register */ _PORT volatile char TOC7M _IO(0x42); /* oc7 mask register */ _PORT volatile char TOC7D _IO(0x43); /* oc7 data register */ _PORT volatile uint TCNT _IO(0x44); /* timer counter */ _PORT volatile char TSCR1 _IO(0x46); /* system control register 1 */ _PORT volatile char TTOV _IO(0x47); /* toggle on overflow register */ _PORT volatile char TCTL1 _IO(0x48); /* control register 1 */ _PORT volatile char TCTL2 _IO(0x49); /* control register 2 */ _PORT volatile char TCTL3 _IO(0x4a); /* control register 3 */ _PORT volatile char TCTL4 _IO(0x4b); /* control register 4 */ _PORT volatile char TIE _IO(0x4c); /* interrupt enable register */ _PORT volatile char TSCR2 _IO(0x4d); /* system control register 2 */ _PORT volatile char TFLG1 _IO(0x4e); /* interrupt flag register 1 */ _PORT volatile char TFLG2 _IO(0x4f); /* interrupt flag register 2 */ _PORT volatile uint TC0 _IO(0x50); /* capture/compare register 0 */ _PORT volatile uint TC1 _IO(0x52); /* capture/compare register 0 */ _PORT volatile uint TC2 _IO(0x54); /* capture/compare register 0 */ _PORT volatile uint TC3 _IO(0x56); /* capture/compare register 0 */ _PORT volatile uint TC4 _IO(0x58); /* capture/compare register 0 */ _PORT volatile uint TC5 _IO(0x5a); /* capture/compare register 0 */ _PORT volatile uint TC6 _IO(0x5c); /* capture/compare register 0 */ _PORT volatile uint TC7 _IO(0x5e); /* capture/compare register 0 */ _PORT volatile char PACTL _IO(0x60); /* pulse accumulator A control */ _PORT volatile char PAFLG _IO(0x61); /* pulse accumulator A flag */ _PORT volatile char PACN3 _IO(0x62); /* pulse accumulator A3 count */ _PORT volatile char PACN2 _IO(0x63); /* pulse accumulator A2 count */ _PORT volatile char PACN1 _IO(0x64); /* pulse accumulator A1 count */ _PORT volatile char PACN0 _IO(0x65); /* pulse accumulator A0 count */ _PORT volatile char MCCTL _IO(0x66); /* modulus counter control reg */ _PORT volatile char MCFLG _IO(0x67); /* modulus counter flag reg */ _PORT volatile char ICPAR _IO(0x68); /* input control pulse acc reg */ _PORT volatile char DLYCT _IO(0x69); /* delay counter control reg */ _PORT volatile char ICOVW _IO(0x6a); /* input control overwrite reg */ _PORT volatile char ICSYS _IO(0x6b); /* input control system reg */ _PORT volatile char TIMTST _IO(0x6d); /* timer test register */ _PORT volatile char PBCTL _IO(0x70); /* pulse accumulator B control */ _PORT volatile char PBFLG _IO(0x71); /* pulse accumulator B flag */ _PORT volatile char PA3H _IO(0x72); /* pulse accumulator B3 count */ _PORT volatile char PA2H _IO(0x73); /* pulse accumulator B2 count */ _PORT volatile char PA1H _IO(0x74); /* pulse accumulator B1 count */ _PORT volatile char PA0H _IO(0x75); /* pulse accumulator B0 count */ _PORT volatile uint MCCNT _IO(0x76); /* modulus counter count reg */ _PORT volatile uint TC0H _IO(0x78); /* timer input capture hold 0 */ _PORT volatile uint TC1H _IO(0x7a); /* timer input capture hold 1 */ _PORT volatile uint TC2H _IO(0x7c); /* timer input capture hold 2 */ _PORT volatile uint TC3H _IO(0x7e); /* timer input capture hold 3 */ /* ATD0 Module */ _PORT volatile char ATD0CTL0 _IO(0x80); /* A/D0 control register 0 */ _PORT volatile char ATD0CTL1 _IO(0x81); /* A/D0 control register 1 */ _PORT volatile char ATD0CTL2 _IO(0x82); /* A/D0 control register 2 */ _PORT volatile char ATD0CTL3 _IO(0x83); /* A/D0 control register 3 */ _PORT volatile char ATD0CTL4 _IO(0x84); /* A/D0 control register 4 */ _PORT volatile char ATD0CTL5 _IO(0x85); /* A/D0 control register 5 */ _PORT volatile char ATD0STAT0 _IO(0x86); /* A/D0 status register 0 */ _PORT volatile char ATD0TEST0 _IO(0x88); /* A/D0 test register 0 */ _PORT volatile char ATD0TEST1 _IO(0x89); /* A/D0 test register 1 */ _PORT volatile char ATD0STAT1 _IO(0x8b); /* A/D0 status register 1 */ _PORT volatile char ATD0DIEN _IO(0x8d); /* A/D0 interrupt enable */ _PORT volatile char PORTAD0 _IO(0x8f); /* port AD0 data input register */ _PORT volatile uint ATD0DR0 _IO(0x90); /* A/D0 result 0 */ _PORT volatile uint ATD0DR1 _IO(0x92); /* A/D0 result 1 */ _PORT volatile uint ATD0DR2 _IO(0x94); /* A/D0 result 2 */ _PORT volatile uint ATD0DR3 _IO(0x96); /* A/D0 result 3 */ _PORT volatile uint ATD0DR4 _IO(0x98); /* A/D0 result 4 */ _PORT volatile uint ATD0DR5 _IO(0x9a); /* A/D0 result 5 */ _PORT volatile uint ATD0DR6 _IO(0x9c); /* A/D0 result 6 */ _PORT volatile uint ATD0DR7 _IO(0x9e); /* A/D0 result 7 */ /* PWM Module */ _PORT volatile char PWME _IO(0xa0); /* PWM Enable */ _PORT volatile char PWMPOL _IO(0xa1); /* PWM Clock Polarity */ _PORT volatile char PWMCLK _IO(0xa2); /* PWM Clocks */ _PORT volatile char PWMPRCLK _IO(0xa3); /* PWM prescale clock select */ _PORT volatile char PWMCAE _IO(0xa4); /* PWM center align enable */ _PORT volatile char PWMCTL _IO(0xa5); /* PWM Control Register */ _PORT volatile char PWMTST _IO(0xa6); /* PWM Test Register */ _PORT volatile char PWMPRSC _IO(0xa7); /* PWM Test Register */ _PORT volatile char PWMSCLA _IO(0xa8); /* PWM scale A */ _PORT volatile char PWMSCLB _IO(0xa9); /* PWM scale B */ _PORT volatile char PWMSCNTA _IO(0xaa); /* PWM Test Register A */ _PORT volatile char PWMSCNTB _IO(0xab); /* PWM Test Register B */ _PORT volatile char PWMCNT0 _IO(0xac); /* PWM Channel Counter 0 */ _PORT volatile char PWMCNT1 _IO(0xad); /* PWM Channel Counter 1 */ _PORT volatile char PWMCNT2 _IO(0xae); /* PWM Channel Counter 2 */ _PORT volatile char PWMCNT3 _IO(0xaf); /* PWM Channel Counter 3 */ _PORT volatile char PWMCNT4 _IO(0xb0); /* PWM Channel Counter 4 */ _PORT volatile char PWMCNT5 _IO(0xb1); /* PWM Channel Counter 5 */ _PORT volatile char PWMCNT6 _IO(0xb2); /* PWM Channel Counter 6 */ _PORT volatile char PWMCNT7 _IO(0xb3); /* PWM Channel Counter 7 */ _PORT volatile char PWMPER0 _IO(0xb4); /* PWM Channel Period 0 */ _PORT volatile char PWMPER1 _IO(0xb5); /* PWM Channel Period 1 */ _PORT volatile char PWMPER2 _IO(0xb6); /* PWM Channel Period 2 */ _PORT volatile char PWMPER3 _IO(0xb7); /* PWM Channel Period 3 */ _PORT volatile char PWMPER4 _IO(0xb8); /* PWM Channel Period 4 */ _PORT volatile char PWMPER5 _IO(0xb9); /* PWM Channel Period 5 */ _PORT volatile char PWMPER6 _IO(0xba); /* PWM Channel Period 6 */ _PORT volatile char PWMPER7 _IO(0xbb); /* PWM Channel Period 7 */ _PORT volatile char PWMDTY0 _IO(0xbc); /* PWM Channel Duty 0 */ _PORT volatile char PWMDTY1 _IO(0xbd); /* PWM Channel Duty 1 */ _PORT volatile char PWMDTY2 _IO(0xbe); /* PWM Channel Duty 2 */ _PORT volatile char PWMDTY3 _IO(0xbf); /* PWM Channel Duty 3 */ _PORT volatile char PWMDTY4 _IO(0xc0); /* PWM Channel Duty 4 */ _PORT volatile char PWMDTY5 _IO(0xc1); /* PWM Channel Duty 5 */ _PORT volatile char PWMDTY6 _IO(0xc2); /* PWM Channel Duty 6 */ _PORT volatile char PWMDTY7 _IO(0xc3); /* PWM Channel Duty 7 */ _PORT volatile char PWMSDN _IO(0xc4); /* PWM shutdown register */ /* SCI0 Module */ _PORT volatile char SCI0BDH _IO(0xc8); /* SCI 0 baud rate high */ _PORT volatile char SCI0BDL _IO(0xc9); /* SCI 0 baud rate low */ _PORT volatile char SCI0CR1 _IO(0xca); /* SCI 0 control register 1 */ _PORT volatile char SCI0CR2 _IO(0xcb); /* SCI 0 control register 2 */ _PORT volatile char SCI0SR1 _IO(0xcc); /* SCI 0 status register 1 */ _PORT volatile char SCI0SR2 _IO(0xcd); /* SCI 0 status register 2 */ _PORT volatile char SCI0DRH _IO(0xce); /* SCI 0 data register high */ _PORT volatile char SCI0DRL _IO(0xcf); /* SCI 0 data register low */ /* SCI1 Module */ _PORT volatile char SCI1BDH _IO(0xd0); /* SCI 1 baud rate high */ _PORT volatile char SCI1BDL _IO(0xd1); /* SCI 1 baud rate low */ _PORT volatile char SCI1CR1 _IO(0xd2); /* SCI 1 control register 1 */ _PORT volatile char SCI1CR2 _IO(0xd3); /* SCI 1 control register 2 */ _PORT volatile char SCI1SR1 _IO(0xd4); /* SCI 1 status register 1 */ _PORT volatile char SCI1SR2 _IO(0xd5); /* SCI 1 status register 2 */ _PORT volatile char SCI1DRH _IO(0xd6); /* SCI 1 data register high */ _PORT volatile char SCI1DRL _IO(0xd7); /* SCI 1 data register low */ /* SPI0 Module */ _PORT volatile char SPI0CR1 _IO(0xd8); /* SPI 0 control register 1 */ _PORT volatile char SPI0CR2 _IO(0xd9); /* SPI 0 control register 2 */ _PORT volatile char SPI0BR _IO(0xda); /* SPI 0 baud rate register */ _PORT volatile char SPI0SR _IO(0xdb); /* SPI 0 status register */ _PORT volatile char SPI0DR _IO(0xdd); /* SPI 0 data register */ /* I2C Module */ _PORT volatile char IBAD _IO(0xe0); /* I2C address register */ _PORT volatile char IBFD _IO(0xe1); /* I2C freqency divider reg */ _PORT volatile char IBCR _IO(0xe2); /* I2C control register */ _PORT volatile char IBSR _IO(0xe3); /* I2C status register */ _PORT volatile char IBDR _IO(0xe4); /* I2C data register */ /* BDLC Module */ _PORT volatile char DLCBCR1 _IO(0xe8); /* BDLC control register 1 */ _PORT volatile char DLCBSVR _IO(0xe9); /* BDLC state vector register */ _PORT volatile char DLCBCR2 _IO(0xea); /* BDLC control register 2 */ _PORT volatile char DLCBDR _IO(0xeb); /* BDLC data register */ _PORT volatile char DLCBARD _IO(0xec); /* BDLC analog round trip delay */ _PORT volatile char DLCBRSR _IO(0xed); /* BDLC rate select register */ _PORT volatile char DLCSCR _IO(0xee); /* BDLC control register */ _PORT volatile char DLCBSTAT _IO(0xef); /* BDLC status register */ /* SPI1 Module */ _PORT volatile char SPI1CR1 _IO(0xf0); /* SPI 1 control register 1 */ _PORT volatile char SPI1CR2 _IO(0xf1); /* SPI 1 control register 2 */ _PORT volatile char SPI1BR _IO(0xf2); /* SPI 1 baud rate register */ _PORT volatile char SPI1SR _IO(0xf3); /* SPI 1 status register */ _PORT volatile char SPI1DR _IO(0xf5); /* SPI 1 data register */ /* SPI2 Module */ _PORT volatile char SPI2CR1 _IO(0xf8); /* SPI 2 control register 1 */ _PORT volatile char SPI2CR2 _IO(0xf9); /* SPI 2 control register 2 */ _PORT volatile char SPI2BR _IO(0xfa); /* SPI 2 baud rate register */ _PORT volatile char SPI2SR _IO(0xfb); /* SPI 2 status register */ _PORT volatile char SPI2DR _IO(0xfd); /* SPI 2 data register */ /* Flash Control Module */ volatile char FCLKDIV _IO(0x100); /* flash clock divider */ volatile char FSEC _IO(0x101); /* flash security register */ volatile char FCNFG _IO(0x103); /* flash configuration register */ volatile char FPROT _IO(0x104); /* flash protection register */ volatile char FSTAT _IO(0x105); /* flash status register */ volatile char FCMD _IO(0x106); /* flash command register */ /* EEPROM Control Module */ volatile char ECLKDIV _IO(0x110); /* eeprom clock divider */ volatile char ECNFG _IO(0x113); /* eeprom configuration register */ volatile char EPROT _IO(0x114); /* eeprom protection register */ volatile char ESTAT _IO(0x115); /* eeprom status register */ volatile char ECMD _IO(0x116); /* eeprom command register */ /* ATD1 Module */ volatile char ATD1CTL0 _IO(0x120); /* A/D1 control register 0 */ volatile char ATD1CTL1 _IO(0x121); /* A/D1 control register 1 */ volatile char ATD1CTL2 _IO(0x122); /* A/D1 control register 2 */ volatile char ATD1CTL3 _IO(0x123); /* A/D1 control register 3 */ volatile char ATD1CTL4 _IO(0x124); /* A/D1 control register 4 */ volatile char ATD1CTL5 _IO(0x125); /* A/D1 control register 5 */ volatile char ATD1STAT0 _IO(0x126); /* A/D1 status register 0 */ volatile char ATD1TEST0 _IO(0x128); /* A/D1 test register 0 */ volatile char ATD1TEST1 _IO(0x129); /* A/D1 test register 1 */ volatile char ATD1STAT1 _IO(0x12b); /* A/D1 status register 1 */ volatile char ATD1DIEN _IO(0x12d); /* A/D1 interrupt enable */ volatile char PORTAD1 _IO(0x12f); /* port AD1 data input register */ volatile uint ATD1DR0 _IO(0x130); /* A/D1 result 0 */ volatile uint ATD1DR1 _IO(0x132); /* A/D1 result 1 */ volatile uint ATD1DR2 _IO(0x134); /* A/D1 result 2 */ volatile uint ATD1DR3 _IO(0x136); /* A/D1 result 3 */ volatile uint ATD1DR4 _IO(0x138); /* A/D1 result 4 */ volatile uint ATD1DR5 _IO(0x13a); /* A/D1 result 5 */ volatile uint ATD1DR6 _IO(0x13c); /* A/D1 result 6 */ volatile uint ATD1DR7 _IO(0x13e); /* A/D1 result 7 */ /* CAN0 Module */ volatile char CAN0CTL0 _IO(0x140); /* CAN0 control register 0 */ volatile char CAN0CTL1 _IO(0x141); /* CAN0 control register 1 */ volatile char CAN0BTR0 _IO(0x142); /* CAN0 bus timing register 0 */ volatile char CAN0BTR1 _IO(0x143); /* CAN0 bus timing register 1 */ volatile char CAN0RFLG _IO(0x144); /* CAN0 receiver flag register */ volatile char CAN0RIER _IO(0x145); /* CAN0 receiver interrupt reg */ volatile char CAN0TFLG _IO(0x146); /* CAN0 transmitter flag reg */ volatile char CAN0TIER _IO(0x147); /* CAN0 transmitter control reg */ volatile char CAN0TARQ _IO(0x148); /* CAN0 transmitter abort request */ volatile char CAN0TAAK _IO(0x149); /* CAN0 transmitter abort acknowledge */ volatile char CAN0TBSEL _IO(0x14a); /* CAN0 transmit buffer selection */ volatile char CAN0IDAC _IO(0x14b); /* CAN0 identifier acceptance */ volatile char CAN0RXERR _IO(0x14e); /* CAN0 receive error counter */ volatile char CAN0TXERR _IO(0x14f); /* CAN0 transmit error counter */ volatile char CAN0IDAR0 _IO(0x150); /* CAN0 id acceptance reg 0 */ volatile char CAN0IDAR1 _IO(0x151); /* CAN0 id acceptance reg 1 */ volatile char CAN0IDAR2 _IO(0x152); /* CAN0 id acceptance reg 2 */ volatile char CAN0IDAR3 _IO(0x153); /* CAN0 id acceptance reg 3 */ volatile char CAN0IDMR0 _IO(0x154); /* CAN0 id mask register 0 */ volatile char CAN0IDMR1 _IO(0x155); /* CAN0 id mask register 1 */ volatile char CAN0IDMR2 _IO(0x156); /* CAN0 id mask register 2 */ volatile char CAN0IDMR3 _IO(0x157); /* CAN0 id mask register 3 */ volatile char CAN0IDAR4 _IO(0x158); /* CAN0 id acceptance reg 4 */ volatile char CAN0IDAR5 _IO(0x159); /* CAN0 id acceptance reg 5 */ volatile char CAN0IDAR6 _IO(0x15a); /* CAN0 id acceptance reg 6 */ volatile char CAN0IDAR7 _IO(0x15b); /* CAN0 id acceptance reg 7 */ volatile char CAN0IDMR4 _IO(0x15c); /* CAN0 id mask register 4 */ volatile char CAN0IDMR5 _IO(0x15d); /* CAN0 id mask register 5 */ volatile char CAN0IDMR6 _IO(0x15e); /* CAN0 id mask register 6 */ volatile char CAN0IDMR7 _IO(0x15f); /* CAN0 id mask register 7 */ volatile char CAN0RXFG[16] _IO(0x160); /* CAN0 receive buffer */ volatile char CAN0TXFG[16] _IO(0x170); /* CAN0 transmit buffer */ /* CAN1 Module */ volatile char CAN1CTL0 _IO(0x180); /* CAN1 control register 0 */ volatile char CAN1CTL1 _IO(0x181); /* CAN1 control register 1 */ volatile char CAN1BTR0 _IO(0x182); /* CAN1 bus timing register 0 */ volatile char CAN1BTR1 _IO(0x183); /* CAN1 bus timing register 1 */ volatile char CAN1RFLG _IO(0x184); /* CAN1 receiver flag register */ volatile char CAN1RIER _IO(0x185); /* CAN1 receiver interrupt reg */ volatile char CAN1TFLG _IO(0x186); /* CAN1 transmitter flag reg */ volatile char CAN1TIER _IO(0x187); /* CAN1 transmitter control reg */ volatile char CAN1TARQ _IO(0x188); /* CAN1 transmitter abort request */ volatile char CAN1TAAK _IO(0x189); /* CAN1 transmitter abort acknowledge */ volatile char CAN1TBSEL _IO(0x18a); /* CAN1 transmit buffer selection */ volatile char CAN1IDAC _IO(0x18b); /* CAN1 identifier acceptance */ volatile char CAN1RXERR _IO(0x18e); /* CAN1 transmitter control reg */ volatile char CAN1TXERR _IO(0x18f); /* CAN1 transmit error counter */ volatile char CAN1IDAR0 _IO(0x190); /* CAN1 id acceptance reg 0 */ volatile char CAN1IDAR1 _IO(0x191); /* CAN1 id acceptance reg 1 */ volatile char CAN1IDAR2 _IO(0x192); /* CAN1 id acceptance reg 2 */ volatile char CAN1IDAR3 _IO(0x193); /* CAN1 id acceptance reg 3 */ volatile char CAN1IDMR0 _IO(0x194); /* CAN1 id mask register 0 */ volatile char CAN1IDMR1 _IO(0x195); /* CAN1 id mask register 1 */ volatile char CAN1IDMR2 _IO(0x196); /* CAN1 id mask register 2 */ volatile char CAN1IDMR3 _IO(0x197); /* CAN1 id mask register 3 */ volatile char CAN1IDAR4 _IO(0x198); /* CAN1 id acceptance reg 4 */ volatile char CAN1IDAR5 _IO(0x199); /* CAN1 id acceptance reg 5 */ volatile char CAN1IDAR6 _IO(0x19a); /* CAN1 id acceptance reg 6 */ volatile char CAN1IDAR7 _IO(0x19b); /* CAN1 id acceptance reg 7 */ volatile char CAN1IDMR4 _IO(0x19c); /* CAN1 id mask register 4 */ volatile char CAN1IDMR5 _IO(0x19d); /* CAN1 id mask register 5 */ volatile char CAN1IDMR6 _IO(0x19e); /* CAN1 id mask register 6 */ volatile char CAN1IDMR7 _IO(0x19f); /* CAN1 id mask register 7 */ volatile char CAN1RXFG[16] _IO(0x1a0); /* CAN1 receive buffer */ volatile char CAN1TXFG[16] _IO(0x1b0); /* CAN1 transmit buffer */ /* CAN2 Module */ volatile char CAN2CTL0 _IO(0x1c0); /* CAN2 control register 0 */ volatile char CAN2CTL1 _IO(0x1c1); /* CAN2 control register 1 */ volatile char CAN2BTR0 _IO(0x1c2); /* CAN2 bus timing register 0 */ volatile char CAN2BTR1 _IO(0x1c3); /* CAN2 bus timing register 1 */ volatile char CAN2RFLG _IO(0x1c4); /* CAN2 receiver flag register */ volatile char CAN2RIER _IO(0x1c5); /* CAN2 receiver interrupt reg */ volatile char CAN2TFLG _IO(0x1c6); /* CAN2 transmitter flag reg */ volatile char CAN2TIER _IO(0x1c7); /* CAN2 transmitter control reg */ volatile char CAN2TARQ _IO(0x1c8); /* CAN2 transmitter abort request */ volatile char CAN2TAAK _IO(0x1c9); /* CAN2 transmitter abort acknowledge */ volatile char CAN2TBSEL _IO(0x1ca); /* CAN2 transmit buffer selection */ volatile char CAN2IDAC _IO(0x1cb); /* CAN2 identifier acceptance */ volatile char CAN2RXERR _IO(0x1ce); /* CAN2 transmitter control reg */ volatile char CAN2TXERR _IO(0x1cf); /* CAN2 transmit error counter */ volatile char CAN2IDAR0 _IO(0x1d0); /* CAN2 id acceptance reg 0 */ volatile char CAN2IDAR1 _IO(0x1d1); /* CAN2 id acceptance reg 1 */ volatile char CAN2IDAR2 _IO(0x1d2); /* CAN2 id acceptance reg 2 */ volatile char CAN2IDAR3 _IO(0x1d3); /* CAN2 id acceptance reg 3 */ volatile char CAN2IDMR0 _IO(0x1d4); /* CAN2 id mask register 0 */ volatile char CAN2IDMR1 _IO(0x1d5); /* CAN2 id mask register 1 */ volatile char CAN2IDMR2 _IO(0x1d6); /* CAN2 id mask register 2 */ volatile char CAN2IDMR3 _IO(0x1d7); /* CAN2 id mask register 3 */ volatile char CAN2IDAR4 _IO(0x1d8); /* CAN2 id acceptance reg 4 */ volatile char CAN2IDAR5 _IO(0x1d9); /* CAN2 id acceptance reg 5 */ volatile char CAN2IDAR6 _IO(0x1da); /* CAN2 id acceptance reg 6 */ volatile char CAN2IDAR7 _IO(0x1db); /* CAN2 id acceptance reg 7 */ volatile char CAN2IDMR4 _IO(0x1dc); /* CAN2 id mask register 4 */ volatile char CAN2IDMR5 _IO(0x1dd); /* CAN2 id mask register 5 */ volatile char CAN2IDMR6 _IO(0x1de); /* CAN2 id mask register 6 */ volatile char CAN2IDMR7 _IO(0x1df); /* CAN2 id mask register 7 */ volatile char CAN2RXFG[16] _IO(0x1e0); /* CAN2 receive buffer */ volatile char CAN2TXFG[16] _IO(0x1f0); /* CAN2 transmit buffer */ /* CAN3 Module */ volatile char CAN3CTL0 _IO(0x200); /* CAN3 control register 0 */ volatile char CAN3CTL1 _IO(0x201); /* CAN3 control register 1 */ volatile char CAN3BTR0 _IO(0x202); /* CAN3 bus timing register 0 */ volatile char CAN3BTR1 _IO(0x203); /* CAN3 bus timing register 1 */ volatile char CAN3RFLG _IO(0x204); /* CAN3 receiver flag register */ volatile char CAN3RIER _IO(0x205); /* CAN3 receiver interrupt reg */ volatile char CAN3TFLG _IO(0x206); /* CAN3 transmitter flag reg */ volatile char CAN3TIER _IO(0x207); /* CAN3 transmitter control reg */ volatile char CAN3TARQ _IO(0x208); /* CAN3 transmitter abort request */ volatile char CAN3TAAK _IO(0x209); /* CAN3 transmitter abort acknowledge */ volatile char CAN3TBSEL _IO(0x20a); /* CAN3 transmit buffer selection */ volatile char CAN3IDAC _IO(0x20b); /* CAN3 identifier acceptance */ volatile char CAN3RXERR _IO(0x20e); /* CAN3 transmitter control reg */ volatile char CAN3TXERR _IO(0x20f); /* CAN3 transmit error counter */ volatile char CAN3IDAR0 _IO(0x210); /* CAN3 id acceptance reg 0 */ volatile char CAN3IDAR1 _IO(0x211); /* CAN3 id acceptance reg 1 */ volatile char CAN3IDAR2 _IO(0x212); /* CAN3 id acceptance reg 2 */ volatile char CAN3IDAR3 _IO(0x213); /* CAN3 id acceptance reg 3 */ volatile char CAN3IDMR0 _IO(0x214); /* CAN3 id mask register 0 */ volatile char CAN3IDMR1 _IO(0x215); /* CAN3 id mask register 1 */ volatile char CAN3IDMR2 _IO(0x216); /* CAN3 id mask register 2 */ volatile char CAN3IDMR3 _IO(0x217); /* CAN3 id mask register 3 */ volatile char CAN3IDAR4 _IO(0x218); /* CAN3 id acceptance reg 4 */ volatile char CAN3IDAR5 _IO(0x219); /* CAN3 id acceptance reg 5 */ volatile char CAN3IDAR6 _IO(0x21a); /* CAN3 id acceptance reg 6 */ volatile char CAN3IDAR7 _IO(0x21b); /* CAN3 id acceptance reg 7 */ volatile char CAN3IDMR4 _IO(0x21c); /* CAN3 id mask register 4 */ volatile char CAN3IDMR5 _IO(0x21d); /* CAN3 id mask register 5 */ volatile char CAN3IDMR6 _IO(0x21e); /* CAN3 id mask register 6 */ volatile char CAN3IDMR7 _IO(0x21f); /* CAN3 id mask register 7 */ volatile char CAN3RXFG[16] _IO(0x220); /* CAN3 receive buffer */ volatile char CAN3TXFG[16] _IO(0x230); /* CAN3 transmit buffer */ /* Port T Module */ volatile char PTT _IO(0x240); /* port T data register */ volatile char PTIT _IO(0x241); /* port T input register */ volatile char DDRT _IO(0x242); /* port T data direction */ volatile char RDRT _IO(0x243); /* port T reduce drive */ volatile char PERT _IO(0x244); /* port T pull enable */ volatile char PPST _IO(0x245); /* port T polarity select */ /* Port S Module */ volatile char PTS _IO(0x248); /* port S data register */ volatile char PTIS _IO(0x249); /* port S input register */ volatile char DDRS _IO(0x24a); /* port S data direction */ volatile char RDRS _IO(0x24b); /* port S reduce drive */ volatile char PERS _IO(0x24c); /* port S pull enable */ volatile char PPSS _IO(0x24d); /* port S polarity select */ volatile char WOMS _IO(0x24e); /* port S wired-or mode */ /* Port M Module */ volatile char PTM _IO(0x250); /* port M data register */ volatile char PTIM _IO(0x251); /* port M input register */ volatile char DDRM _IO(0x252); /* port M data direction */ volatile char RDRM _IO(0x253); /* port M reduce drive */ volatile char PERM _IO(0x254); /* port M pull enable */ volatile char PPSM _IO(0x255); /* port M polarity select */ volatile char WOMM _IO(0x256); /* port M wired-or mode */ /* Port P Module */ volatile char PTP _IO(0x258); /* port P data register */ volatile char PTIP _IO(0x259); /* port P input register */ volatile char DDRP _IO(0x25a); /* port P data direction */ volatile char RDRP _IO(0x25b); /* port P reduce drive */ volatile char PERP _IO(0x25c); /* port P pull enable */ volatile char PPSP _IO(0x25d); /* port P polarity select */ volatile char PIEP _IO(0x25e); /* port P interrupt enable */ volatile char PIFP _IO(0x25f); /* port P interrupt flag */ /* Port H Module */ volatile char PTH _IO(0x260); /* port H data register */ volatile char PTIH _IO(0x261); /* port H input register */ volatile char DDRH _IO(0x262); /* port H data direction */ volatile char RDRH _IO(0x263); /* port H reduce drive */ volatile char PERH _IO(0x264); /* port H pull enable */ volatile char PPSH _IO(0x265); /* port H polarity select */ volatile char PIEH _IO(0x266); /* port H interrupt enable */ volatile char PIFH _IO(0x267); /* port H interrupt flag */ /* Port J Module */ volatile char PTJ _IO(0x268); /* port J data register */ volatile char PTIJ _IO(0x269); /* port J input register */ volatile char DDRJ _IO(0x26a); /* port J data direction */ volatile char RDRJ _IO(0x26b); /* port J reduce drive */ volatile char PERJ _IO(0x26c); /* port J pull enable */ volatile char PPSJ _IO(0x26d); /* port J polarity select */ volatile char PIEJ _IO(0x26e); /* port J interrupt enable */ volatile char PIFJ _IO(0x26f); /* port J interrupt flag */ /* CAN4 Module */ volatile char CAN4CTL0 _IO(0x280); /* CAN4 control register 0 */ volatile char CAN4CTL1 _IO(0x281); /* CAN4 control register 1 */ volatile char CAN4BTR0 _IO(0x282); /* CAN4 bus timing register 0 */ volatile char CAN4BTR1 _IO(0x283); /* CAN4 bus timing register 1 */ volatile char CAN4RFLG _IO(0x284); /* CAN4 receiver flag register */ volatile char CAN4RIER _IO(0x285); /* CAN4 receiver interrupt reg */ volatile char CAN4TFLG _IO(0x286); /* CAN4 transmitter flag reg */ volatile char CAN4TIER _IO(0x287); /* CAN4 transmitter control reg */ volatile char CAN4TARQ _IO(0x288); /* CAN4 transmitter abort request */ volatile char CAN4TAAK _IO(0x289); /* CAN4 transmitter abort acknowledge */ volatile char CAN4TBSEL _IO(0x28a); /* CAN4 transmit buffer selection */ volatile char CAN4IDAC _IO(0x28b); /* CAN4 identifier acceptance */ volatile char CAN4RXERR _IO(0x28e); /* CAN4 transmitter control reg */ volatile char CAN4TXERR _IO(0x28f); /* CAN4 transmit error counter */ volatile char CAN4IDAR0 _IO(0x290); /* CAN4 id acceptance reg 0 */ volatile char CAN4IDAR1 _IO(0x291); /* CAN4 id acceptance reg 1 */ volatile char CAN4IDAR2 _IO(0x292); /* CAN4 id acceptance reg 2 */ volatile char CAN4IDAR3 _IO(0x293); /* CAN4 id acceptance reg 3 */ volatile char CAN4IDMR0 _IO(0x294); /* CAN4 id mask register 0 */ volatile char CAN4IDMR1 _IO(0x295); /* CAN4 id mask register 1 */ volatile char CAN4IDMR2 _IO(0x296); /* CAN4 id mask register 2 */ volatile char CAN4IDMR3 _IO(0x297); /* CAN4 id mask register 3 */ volatile char CAN4IDAR4 _IO(0x298); /* CAN4 id acceptance reg 4 */ volatile char CAN4IDAR5 _IO(0x299); /* CAN4 id acceptance reg 5 */ volatile char CAN4IDAR6 _IO(0x29a); /* CAN4 id acceptance reg 6 */ volatile char CAN4IDAR7 _IO(0x29b); /* CAN4 id acceptance reg 7 */ volatile char CAN4IDMR4 _IO(0x29c); /* CAN4 id mask register 4 */ volatile char CAN4IDMR5 _IO(0x29d); /* CAN4 id mask register 5 */ volatile char CAN4IDMR6 _IO(0x29e); /* CAN4 id mask register 6 */ volatile char CAN4IDMR7 _IO(0x29f); /* CAN4 id mask register 7 */ volatile char CAN4RXFG[16] _IO(0x2a0); /* CAN4 receive buffer */ volatile char CAN4TXFG[16] _IO(0x2b0); /* CAN4 transmit buffer */ #undef uint