PEAR: 	equ		$000a
MODE: 	equ		$000b
EBICTL: equ		$000e
INITRM: equ		$0010
MISC: 	equ		$0013
SYNR: 	equ		$0034
REFDV: 	equ		$0035
CRGFLG: equ		$0037
CLKSEL: equ		$0039
COPCTL: equ		$003c
ARMCOP: equ		$003f

exp_in:  equ		$4000
exp_out: equ		$4001
	
	org 	$400
; Set bus clock to 24 MHz
	bclr 	CLKSEL,#$80 ; Use oscillator rather than PLL
	movb 	#$03,REFDV ; Set clock divider to 4
	movb 	#$05,SYNR ; Set clock multiplier to 6
l1:	brclr 	CRGFLG,#$08,l1 ; Wait for PLL to lock
	bset 	CLKSEL,#$80 ; Switch to PLL

; Put into expanded mode
	movb 	#$e8,MODE ; Expanded wide mode, IV on
	movb 	#$0c,PEAR ; Turn on R/W, LSTRB, E
	movb 	#$01,EBICTL ; Use E-clock to control external bus
	movb 	#$03,MISC ; No E-clock stretch, disable ROM from 4000-7FFF

l2:	brclr   exp_in,#$1,l3  ; Check Button 1
	incb                   ; If high, increment
	bra	l4
l3:     decb                   ; If low, decrement
l4:	stab	exp_out        ; Store in output port
	ldy	#$ffff         ; Delay a bit
	dbne	y,*
	bra		l2