EE 308
Homework #8
Due Mar. 17, 1997

1. Design an address-data demultiplexer and an address decoder using an Altera 7032. In addition to the inputs from the HC11 your design should have an input called EXP_ENn. When this input is low, the outputs from the chip are enabled. When this input is high, the outputs are disabled. This input allows you to disable the expansion so you can use the chip in single-chip mode when you need to.

   The design should have the following outputs:

   A[7..0]	Latched low byte of address
   CS_MEMn	Low when 0x2000 <= A[15..0] <= 0x9FFF, E is high, and EXP_ENn is low.
   CS_PIAn	Low when 0xB000 <= A[15..0] <= 0xB003, and EXP_ENn is low.
   CS_2n	Low when 0xB100 <= A[15..0] <= 0xB1FF, E is high, and EXP_ENn is low.
   CS_3n	Low when 0xB200 <= A[15..0] <= 0xB2FF, E is high, and EXP_ENn is low.
   CS_4n	Low when 0xB300 <= A[15..0] <= 0xB3FF, E is high, and EXP_ENn is low.
   CS_5n	Low when 0xB400 <= A[15..0] <= 0xB4FF, E is high, and EXP_ENn is low.
   OEn	Low when E is high and R_W is high.
   WEn	Low when E is high and R_W is low.

   Here is the beginning of the Altera program:

   TITLE "Memory Expansion Decoder and Address Demultiplexer";
   
   SUBDESIGN memexp
   (
       E           :  INPUT;   % E-Clock %
       R_W         :  INPUT;   % R/W Line %
       AS          :  INPUT;   % Address Strobe %
       EXP_ENn     :  INPUT;   % Memory expansion enabled if low, %
                               % disabled if high %
   
       AD[7..0]    :  INPUT;   % Address/Data lines from HC11 %
   
       A8          :  INPUT;   % High-order address lines from HC11 %
       A9          :  INPUT;
       A10         :  INPUT;
       A11         :  INPUT;
       A12         :  INPUT;
       A13         :  INPUT;
       A14         :  INPUT;
       A15         :  INPUT;
   
       OEn         :  OUTPUT;  % Output Enable to memory %
       WEn         :  OUTPUT;  % Write Enable to memory %
   
       CS_MEMn     :  OUTPUT;  % Chip Select for 32k RAM %
       CS_PIAn     :  OUTPUT;  % Chip Select for 68B21 PIA %
       CS_2n       :  OUTPUT;  % Chip Select for future expansion B100 -- B1FF %
       CS_3n       :  OUTPUT;  % Chip Select for future expansion B200 -- B2FF %
       CS_4n       :  OUTPUT;  % Chip Select for future expansion B300 -- B3FF %
       CS_5n       :  OUTPUT;  % Chip Select for future expansion B400 -- B4FF %
   
   
       A0          :  OUTPUT;  % Demultiplexed low-order address bits % 
       A1          :  OUTPUT; 
       A2          :  OUTPUT;
       A3          :  OUTPUT;
       A4          :  OUTPUT;
       A5          :  OUTPUT;
       A6          :  OUTPUT;
       A7          :  OUTPUT;
   )
   

2. Have your HC11 EVBU wirewrapped and ready for testing.