%*********************************************************************** lpt.tdf - replacement LPT port for the PC-104 bus Bill Rison, 8/30/06 ************************************************************************% TITLE "LPT port on PC-104 Card"; CONSTANT DATA = H"278"; CONSTANT STATUS = H"279"; CONSTANT CONTROL = H"27a"; SUBDESIGN lpt ( %-- PC Bus Signals --% address[9..0] : INPUT; pc_data[7..0] : BIDIR; ior, iow : INPUT; aen : INPUT; irq5 : BIDIR; reset : INPUT; %-- LPT Port Signals --% data[7..0] : BIDIR; control[3..0] : OUTPUT; status[7..3] : INPUT; ) VARIABLE data_latch[7..0] : DFFE; control_latch[5..0] : DFFE; pc_data_buffer[7..0] : TRI; data_buffer[7..0] : TRI; irq_buffer : TRI; BEGIN DEFAULTS %--All DFFE's are not enabled by default --% data_latch[].ena = GND; control_latch[].ena = GND; %--All tri-state buffers are not enabled by default --% pc_data_buffer[].oe = GND; data_buffer[].oe = GND; END DEFAULTS; %-- Code to latch data into data latch --% data_latch[].clrn = !reset; % Clear all bits to zero on reset % data_latch[].d = pc_data[]; data_latch[].clk = iow; data_latch[].clk = iow; if ((address[] == DATA) AND (aen == GND)) then data_latch[].ena = VCC; END IF; %-- Bidirectional data port -- enabled by bit 4 of control DFFE's --% %-- On reset, bit 4 of control latch is low, and data port is output --% data_buffer[].oe = !control_latch[4].q; data_buffer[].in = data_latch[].q; data[] = data_buffer[].out; %-- Code to latch data into control latch --% control_latch[].clrn = !reset; % Clear all bits to zero on reset % control_latch[].d = pc_data[5..0]; control_latch[].clk = iow; if ((address[] == CONTROL) AND (aen == GND)) then control_latch[].ena = VCC; END IF; %-- Some of the control lines are inverted on the connector --% control[0] = !control_latch[0].q; control[1] = !control_latch[1].q; control[2] = control_latch[2].q; control[3] = !control_latch[3].q; %-- Read from data pins on connector --% if ((address[] == DATA) AND (aen == GND) AND (ior == GND)) then pc_data_buffer[].in = data[]; pc_data_buffer[].oe = VCC; end if; %-- Read from status pins on connector -- one status pin is inverted --% if ((address[]==STATUS) AND (aen==GND) AND (ior==GND)) then pc_data_buffer[7].in = !status[7]; pc_data_buffer[6..3].in = status[6..3]; pc_data_buffer[2..0].in = VCC; pc_data_buffer[].oe = VCC; end if; %-- Read from control DFFE's --% %-- (not from control pins, some of which are inverted) --% if ((address[] == CONTROL) AND (aen == GND) AND (ior == GND)) then pc_data_buffer[7..6].in = VCC; pc_data_buffer[5..0].in = control_latch[5..0].q; pc_data_buffer[].oe = VCC; end if; pc_data[] = pc_data_buffer[].out; %-- Interrupt comes from status bit 6 --% %-- Interrupt enable controlled by bit 4 of control --% %-- On reset, bit 4 of control is low, so interrupts are disabled --% irq_buffer.oe = control_latch[4].q; irq_buffer.in = status[6]; irq5 = irq_buffer.out; END;