module parallel_port(io_r,io_w,aen,addr,pc_data,data_port, control_port,status_portirq); input io_r; input io_w; input aen; input [9:0] addr; inout [7:0] pc_data; inout [7:0] data_port; output [3:0] control_port; input [4:0] status_port; inout irq; reg [7:0] internal_bus; wire board_read; reg [7:0] data_reg; reg [5:0] control_reg; always @ (posedge io_w) begin if (aen == 0) begin case (addr) 10'h378: data_reg <= pc_data; 10'h37a: control_reg <= pc_data[5:0]; endcase end end always @(addr, data_port, status_port, control_reg) case (addr) 10'h378: internal_bus = data_port; 10'h379: begin internal_bus[7] = !status_port[4]; internal_bus[6:3] = status_port[3:0]; internal_bus[2:0] = 3'b111; end 10'h37a: begin internal_bus[5:0] = control_reg; internal_bus[7:6] = 2'b11; end default: internal_bus[7:0] = 8'hxx; endcase assign board_read = ((addr >= 10'h378) && (addr <= 10'h37a) && (aen == 0) && (io_r == 0)) ? 1'b1 : 1'b0; assign data_port = control_reg[5] ? 8'bz : data_reg; assign control_port[0] = ~control_reg[0]; assign control_port[1] = ~control_reg[1]; assign control_port[2] = control_reg[2]; assign control_port[3] = ~control_reg[3]; assign irq = control_reg[4] ? status_port[3] : 1'bz; assign pc_data = board_read ? internal_bus : 8'bz; endmodule