In this lab we will implement a 4-bit couter that counts from 0 to F in hex repeatedly and displays the count value on a 7-segment LED display. For each hex value you will need to determine which of the 7 LEDs need to light up to display it. For the prelab, complete a truth table for the MAN74 seven-segment LED. To do this you'll need to make a truth table (like the one started in class last week) with a column for each bit in the 4-bit counter (A, B, C, D), a column for the corresponding hex values (0 through F), and a column for each of the outputs a through g which drive the LEDs in the MAN-74. A HI signal turns on the LED, a LO turns it off. You will need to fill in ones and zeros in the a through g columns corresponding to which LEDs need to be lit to display the desired symbol.

(end of pre-lab)

This lab is under redevelopment for the new Quartus software. It will be posted as soon as possible. Go ahead and get the prelab done and check back later. for the rest of the instructions.

This purpose of this lab exercise is to familiarize you with the Altera/Quartus programming environment’s ability to link two or more design files together into a larger master design. You will create a circuit which will integrate a 4 bit counter (from a graphics design file) with a decoder (from a text design file) into a new project to control a MAN74 7-segment LED display. You will demonstrate the MAN74 counting from 0 to F repeatedly, with direction selection (counting up or down) and reset control.

There are a few important considerations for this lab:

• For this lab you will need to be careful to switch projects when you start on a new one. If you finish a project and start a new file for a new project without setting a new project name your new file will be associated with the old project! Generally it is safer to just quit the Quartus program completely between projects.
• You should make a new folder for today's lab, and within that folder you'll make a folder for each of the three projects we create (counter, decoder, lab11).
• This lab assumes you remember, or can go back and look up, the procedures we used for last week's lab 10. Here we will highlight what material is new, namely the integration of several projects into one master project, while much of the creation of the individual component projects will be review from lab 10.

Figure 1: Block Diagram for 0 to F Counter/Decoder/Display

Part I

In this part of the lab, you will create a graphics design file for a 4-bit counter.

1. Create a separate directory called "Lab10" which you will use as the working directory for this lab. Be sure to save all your work from this lab into this directory.
2. Load the Quartus software and create a new project. Use "counter" for the project name in Part I of this lab. Use the same specs as last week, including the device type EPM7064SLC44-10.
3. Create a Block Diagram File which will define the 4-bit counter. Altera provides primitives and macrofunctions that you can use in your design file.
   1. First, create a new file by choosing New from the File menu. Select Block Diagram/Schematic File This will have a .bdf extension. and OK. An untitled Graphic Editor window opens.
   2. Now is a good time to name this file, so choose File:Save and by default it will give this file a name that matches your project name. Note: The file name and project name must have the same prefix. In this case, the file name should be counter.bdf, and you should put it in a folder called "counter".
4. Place the counter device symbol in your design. This will insert the a 4-bit ripple counter.
   1. Edit: Insert Symbol (or double click in white work space). A "Symbol" window open.
   2. Choose "Others" library then "MAXPlus2" folder.
   3. Scroll down and find "4count", select it and click OK. (For future reference, you can simply type "4count" in the Name box without searching the library.)
   4. The 4COUNT symbol is now attached to the mouse cursor with its upper left corner at the insertion point. Use the left mouse button to place it on the page. Notice that the symbol is outlined in blue to indicate that it is presently selected. Deselect it by clicking the mouse outside of the selected symbol. In a bdf file the snap-to function is automatically enabled to help you align symbols on the page. Adjustments for this behavior are possible but in general you shouldn't need to change them.
5. Now you are ready to create your input and output pins. The counter you are working with requires these signals to be attached to it: clock, count direction (down or up) and the 4-bit output. There are other pins located on this counter, but for this lab we will not require them. To enter the required signals on your schematic:
   1. Double-click the mouse in a blank part of the work area to display the Enter Symbol dialog box. Type "INPUT" in the Symbol Name box, and choose OK. A generic INPUT symbol is displayed. (Rather than typing the name you can find the input pin in the "Primitives" library, "Pin" folder.)
   2. Repeat this process so that you have a total of 3 input signals (or simply copy and paste the input symbol 2 more times), and place them to the left of the 4count symbol
   3. Create four OUTPUT pin symbols using the same method you used for inputs. Place them to the right of the 4COUNT symbol.
   4. Name the input pins.
      • Point to the default pin name "PIN NAME" of one of the input symbols and double click the left mouse button. "PIN NAME" will become highlighted. Type "Clock" as a replacement for "PIN NAME".
      • Similarly, name another input symbol "Down_Up". This signal will allow you to control the direction the device counts.
      • Name the last input symbol "Reset" for the counter’s clear input.
      • Name the output by clicking on the output’s "PIN NAME" as you did for the inputs. Since they correspond to the four count bits, label each one by the bit number: Count0, Count1, Count2, and Count3.
   5. Connecting the pins
      1. Connect the inputs to their proper pins by simply dragging the input pin and moving it over to touch the appropriate pin stub on the counter. Repeat for the other input signals. "Down_up" connects to DNUP, "Reset" connects to CLRN, "Clock" connects to CLK. If you want to move the inputs around for readability, a wire will automatically be drawn as you drag input and move it. (This is the rubberbanding feature, which is on by default). The following signals should now be attached to the proper "4COUNT" pins.
      2. Do the same for your output pins. Be careful to connect them in the proper order. Count0 is our least significant bit (LSB) while on the 4count symbol the LSB is QA. So connections should be as follows: Count0 to QA, Count1 to QB, Count2 to QC, and Count3 to QD.
6. Compile your program. The compilation report will display when a successful compilation is achieved.
7. Simulate your program:
   1. See last week's Lab 10 instructions for how to create the vwf simulation file. Use the default name which should match your project name "counter".
      • Set an End Time of 32us
      • View:Fit in Window to show the entire duration in the window. (kwyboard shortcut is Crrl-W)
   2. Inserting nodes into the simulation
      • Edit:Insert node or bus Refer to Lab 10 for details if you don't remember how to do this.
      • In the Node Finder, list nodes and "copy all" to add all of the nodes to the simulation.
      • Make these modifications to your input signals (Highlight part of signal to be modified, Edit:value or use icon buttons in the left margin of the waveform window to overwrite):
        • Reset should be high until the 30.0us mark, low thereafter.
        • Down_Up should be high until the 16us mark, low thereafter.
        • Overwrite the clock for the entire duration of the simulation, use 1us for the period.
   3. Combine count outputs into a group for easy display of their combined value.
      • By default these are in order of Count0 to Count3. Rearrange by dragging so they are in the opposite order from 3 to 1.
      • Hold the control key while clicking on each to select all four count outputs.
      • Right-click on the selected outputs, select "Group"
      • Name = "Count[3..0]", Radix = Hexadecimal
      • The Count[3..0] now shows as a single line with the equivalent value of the count. The plus sign indicates that it is a group of signals which can be expanded/collapsed by clicking on the +/- icon. For this step expand the group so that the individual components are visible.
   4. Simulate: Ctrl-i or Processing: Start Simulation or use the blue ~> play icon.
   5. Verify that the counter is working correctly. Observe the count values and see that it reverses and resets when the Down_Up and Reset inputs change.
   6. Print out a copy of your .bdf file and paste it in your notebook. The default settings usually work fine for this.
8. Create a symbol from your bdf file: The .bdf file you have just created will be incorporated into another project later. In order to do this, you will have to create a Block Symbol File (.bsf) that represents this creation. The symbol you create can be used like any other macrofunction symbol in a Block Diagram File that is at a higher level in the project hierarchy. To create this symbol:
   1. Click the counter.bdf tab to display the bdf file.
   2. File: Create/Update: Create symbol files for current file
   3. Click OK to the creation message. Your symbol file has been created. For some types of design files, a symbol may have been created when you first saved the file. If so, you will get a message asking whether it is OK to overwrite the existing symbol. Choose OK to ensure that you have the most up-to-date information in your Symbol File.
9. That concludes this project. You must close this project before you start another, generally the best way to ensure this is to quit the Quartus program and start over from scratch in Part II.

Questions for Part I:

1. When setting up your simulation file, how does specifying "groups" instead of "outputs" affect the data provided by the simulation?

    

2. Describe how the reset signal affects the output of your counter.

    

3. Describe what happens when the Down_Up signal is toggled.

    

Part II

In this section we're going to build a decoder that translates the 4-bit counter value to the proper 7-bit a through g outputs necessary to drive the 7-segment LED display. The inputs to this system are the Count0 through Count3 outputs from the counter you just built in Part 1, the outputs are the LED channels a through g.

We need to start a new project at this point, so if you didn't exit out at the end of part one, quit Quartus and re-open it. At this point, you should not have any files open on the Quartus desktop. (You can also start a new project and it will ask if you want to close the old one. Just BE SURE you do not do the next steps while still in the previous "counter" project.) Refer back to lab 10 and part 1 above to recall how to do these steps.

1. Create a new project and name it "decoder" which is the name you will give to the files within the project as well, and save them all in a folder called "decoder".
2. Create an AHDL text design file to define the truth table for a hexadecimal to seven segment LED decoder. Follow the example in Figure 2 when creating this file. The beginning and end of the file have been provided, you will need to fill in the decoder rows according to the table you generated for the prelab.

   SUBDESIGN decoder
   (
   Count0,Count1,Count2,Count3 :INPUT;
   a,b,c,d,e,f,g :OUTPUT;
   )
   BEGIN

   TABLE

   Count3, Count2, Count1, Count0 => a, b, c, d, e, f, g;
   0, 0, 0, 0 => 1, 1, 1, 1, 1, 1, 0;
   0, 0, 0, 1 => 0, 1, 1, 0, 0, 0, 0;
   . . . . . . .
   . . . . . . .
   . . . . . . .
   1, 1, 1, 0 => 1, 0, 0, 1, 1, 1, 1;
   1, 1, 1, 1 => 1, 0, 0, 0, 1, 1, 1;

   END TABLE;

   END;
   Figure 2: AHDL File for Seven Segment LED Decoder

3. Be sure to name your four inputs the same as you named the outputs from the counter file you created in Part I. If you don’t, your files will not be able to "talk to each other" later.
4. When you are finished with your decoder AHDL file, save and compile as usual.
5. Simulate your decoder
   • Create a vector waveform file
   • When you enter nodes, select the group "Count" and outputs a through g. You do not need to insert the intermediate Count0 through Count3 nodes.
   • Set end time to 16us, and fit view to window (Ctrl-w).
   • This time you will need to overwrite the count value with a hex count. Select the "count" input grouping and assign it appropriate values:
     • Edit: Value: Count value the "Count Value" window opens
     • Set radix to Hexadecimal
     • Start value = 0000
     • Increment by 1
   • Select "Timing" tab
     • Start time = 0
     • End time = 16us
     • Count every 1us
   • Save file to default project name in the same directory.
   • Simulate
   • Verify that the outputs agree with the truth table you created for the pre-lab.
   • Print out a copies of your AHDL and simulation files and paste them in your notebook
   • Have a lab assistant verify your results before proceeding.
   • Create a symbol file for this decoder like you did for the counter in Part I.

Question for Part II:

1. What is the obvious advantage for using a truth table format as opposed to Boolean equations for every output when designing an AHDL file to decode binary numbers to a 7 segment display?

Part III

You will now create a .bdf file to link your two previous files together. Again, make sure you are working in the proper directory. This file will be referred to as the Top Level bdf. Before starting, change your project to "lab11". Create a new .bdf file and name it "lab11.bdf". You will now grab the other two files (symbol files) you created in Parts I and II and incorporate them into this file. Do this by selecting Symbol and Enter Symbol from the menu bar. Then type in (or select from the list) the symbol files you created. This will bring up a symbol for each file, and you can place these where ever is convenient on the desktop. You will need to insert and label input and output symbols for any pins that are physically on the EPLD (as you did in Part I). The inputs to the EPLD will be the clock, reset, and down/up signals. The outputs will be the 7 control lines that will attach the EPLD to the 7 segment decoder. Internal signals, such as Count0, Count1, Count2, Count3, and the bus Count(3..0) do not need symbols attached, but their wires must be drawn (extended) and they must be properly named. The internal lines do not have to be physically attached, since the software will recognize connectivity through the similar names (like you did in the 4-bit counter file). Once you are done with this bdf, save and compile it. 

From the Max+plus II menu, select Hierarchy Display. This will show you how your files are integrated together to form one project.
 
 

Question for Part III:

1. List some advantages of creating and simulating a design project in separate parts (like the first two parts in this lab) instead of all in one design file.

Part IV

Create a simulation file that covers the entire project. Name it the same name as your overall project (i.e. - lab11.scf). Set the file size and grid spacing so that 40 complete clock cycles can be observed. When choosing these parameters, consider the following: The input signals you should be concerned with are the clocking, reset, and up/down signals. (Do not select the other input options, if any are given). Refer to Part I for help in selecting the input signals you wish to display, and how to configure each one (i.e. - Down_Up should be high until 3.5us, low elsewhere, etc.). The only output signals you are concerned with are the outputs from the decoder truth table. Run the simulation file, and take note of a few input/output relationships to check for accuracy. You don’t have to check every single one! Fold the simulation and paste it in your lab book.

After you are satisfied that this simulation is correct, print out a copy of your top level .bdf file and paste it in your notebook. Load up the report file for this part of the lab, add your name to it, and print out a selected area that includes the chip pin assignments. This is the schematic diagram for your circuit, put this in your lab book and use it as a wiring reference.
 

Question for Part IV:

1. Why are you being asked to simulate (and verify) each part of this project before you proceed to the next part?

Part V

Program an Altera EPM7032LC44-15T PLD with your lab11.pof file. Build the circuit. Connect the clock input to the TTL signal on your protoboard, and wire the the Down_Up and Reset inputs to logic switches. Connect the seven outputs through current limiting resistors to the appropriate inputs on the MAN74. The LEDs that make up the MAN74 are designed to operate at 20 mA.  As such, choose any resistor values between 250W and 1KW  to limit current through the LED.

After you have the counter wired and working properly, demonstrate it to the Instructor or TA and have them initial here.______

You will also need to bring your chip to the demo unit at the logic analyzer station to print a waveform of your project's output. Get assistance from the instructor or TA for this part of the process. Further instructions can be found at the end of Lab 10