EE 212 Lab
Lab 13: Step Responses of RC and RLC Circuits

In this lab step responses of RC and RLC circuits will be generated and studied.

1. Construct the circuit shown in figure 1.

• Generate a step input, vin(t) = u(t), by using a 1V square wave with a period sufficiently long (i.e., at least 10t) so that the output reaches steady-state before the input transitions.
• Sketch the response and  record the specified step response metrics of figure 2 in a table similar to the following.  Compare the predicted and measured values.

 Predicted Measured Initial Value, vout(0) Final (steady-state) Value, vout,ss = vout(¥) 10% - 90% Rise Time, Tr (Within 5%) Settling Time, Ts Percent Overshoot, 100%(peak value - vout,ss) / vout,ss Time Constant, t

2. Determine values of R, L, and C for the circuit shown in figure 3 so that the step response is a damped sinusoid with an exponential decay governed by a s of 10(i.e. the damped sinusoidal response goes to e-1 of its final value in 10 m-seconds) and a frequency of 1MHz. Use the value of L in your parts kit, i.e., 0.47mH or 0.68mH.

• Observe the step response and compare the theoretical response with your measurements in a table similar to that shown below. For this underdamped RLC circuit, the response should have the form vout(t) = vout,ss (1 - e-stcos(wt + q))u(t).

 Predicted Measured Initial Value Final Value Rise Time Settling Time (within 5%) Percent Overshoot s w