In this lab step responses of RC and RLC circuits will be generated and studied.

1. Construct the circuit shown in figure 1.

- Generate a step input, v
_{in}(t) = u(t), by using a 1V square wave with a period sufficiently long (i.e., at least 10t) so that the output reaches steady-state before the input transitions. - Sketch the response and record the specified step response metrics
of figure 2 in a table similar to the following. Compare the predicted and measured values.

Predicted | Measured | |

Initial Value, v_{out}(0) |
||

Final (steady-state) Value, v_{out,ss} = v_{out}(¥) |
||

10% - 90% Rise Time, T_{r} |
||

(Within 5%) Settling Time, T_{s} |
||

Percent Overshoot, 100%(peak
value - v_{out,ss})
/ v_{out,ss} |
||

Time Constant, t |

2. Determine values of R, L, and C for the circuit
shown in figure 3 so that
the step response is a damped sinusoid with an exponential decay governed by a s
of 10^{5 }(i.e. the damped sinusoidal
response goes to e^{-1} of its final value in 10 m-seconds)
and a frequency of 1MHz.
Use the value of L in your parts kit, i.e., 0.47mH or 0.68mH.

- Observe the step response and compare the theoretical response with
your measurements in a table similar to that shown below. For this underdamped
RLC circuit, the response should have the form v
_{out}(t) = v_{out,ss}(1 - e^{-st}cos(wt + q))u(t).

Predicted | Measured | |

Initial Value | ||

Final Value | ||

Rise Time | ||

Settling Time (within 5%) | ||

Percent Overshoot | ||

s | ||

w |

© Copyright 2003 New Mexico Institute of Mining and Technology