3.1 Introduction to Verilog

- In order to write an Verilog HDL description of any circuit
you will need to write a
*module*which is the fundamental descriptive unit in Verilog. A*module*is a set of text describing your circuit and is enclosed by the keywords**module**and**endmodule**. - As the program describes a physical circuit you will need to
specify the inputs, the outputs, the behavior of the circuit
and how the gates are wired. To accomplish this, you need
the keywords
**input**,**output**, and**wire**to define the inputs, outputs and the wiring between the gates, respectively. - There are multiple ways to model a circuit
- gate-level modeling,
- dataflow modeling,
- behavioral modeling,
- or a combination of the above.

- A simple program modeling a circuit (see
Figure 2) at the gate-level, is provided below.
- As seen above the outputs come first in the port list followed by
the inputs.
- Single line comments begin with //
- Multi-line comments are enclosed by /* */
- Verilog is case sensitive.
- A simple program modeling a circuit using dataflow, is
provided below.
- You can identifiers describing multiple bits known as
*vectors*. For example you may write Program 2 asIn this example, we have the input as three bits representing

`A, B, C`and we have denoted them as`[0:2] X`which means we have three bits with the index 0 representing the MSB. We could have specified it as`[2:0] X`in which case the index 2 represents the MSB. - Given an identifier
`[7:0] X`you can assign it values by`assign [7:0] X = 8'b00101011;`where the

`8'b`specifies that we are defining an 8-bit binary number and`00101011`is that 8-bit binary number. You can also assign parts of the number as`assign [2:0] X = 3'b101;`which assigns only the last three bits of

`X`.

Last Modified 2008-09-16