Up: Lab 5: Arithmetic Logic
Previous: 2 Lab
Subsections
3 Supplementary Material
3.1 Verilog
Parameters are constants and not variables.
parameter num = 8;
assign y = sel?a:b;
If sel is true, then y is assigned a, else
it is assigned b.
In Verilog it is possible to concatenate bits using
.
a, b, c, a, b, c
is equivalent to
a, b, c
assign y = a>b?a:b;
assign y to a if a>b and assign it
to b otherwise. Table 2 shows a list of comparison
operators.
Table 2:
Comparison Operators
Operator 
Description 

greater than 

less than 

greater than or equal to 

less than or equal to 

equality 

equality including x and z 

inequality 

inequality including x and z 
 for
and
the result is x, if either operand
contains an x or z.
Table 3 shows a list of logical operators.
Table 3:
Logical Operators
Operator 
Description 

logical negation 

logical AND 

logical OR 
 Evaluation is performed left to right.
 x if any of the operands has unknown x bits.
Table 4 shows a list of arithmetic operators.
Table 4:
Arithmetic Operators
Operator 
Description 

addition 

subtraction 

multiplication 

division (truncates any fractional part) 

equality 
Table 5 shows a list of unary arithmetic operators.
Table 5:
Unary Arithmetic Operators
Operator 
Description 

Change the sign of the operand 
Table 6 shows a list of bitwise operators.
Table 6:
Bitwise Operators
Operator 
Description 

Bitwise negation 

Bitwise AND 

Bitwise OR 

Bitwise NAND 

Bitwise OR 
or
Equivalence 

Table 7 shows a list of unary reduction operators.
They produce a single bit result by applying the operator to all of the
pits of the operand.
Table 7:
Unary Reduction Operators
Operator 
Description 

Bitwise negation 

Bitwise AND 

Bitwise OR 

Bitwise NAND 

Bitwise OR 
or
Equivalence 

Table 8 shows a list of shift operators.
Table 8:
Shift Operators
Operator 
Description 

left shift 

right shift 
 Left operand is shifted by the number of bit positions given by
the right operand.
 Zeros are used to fill vacated bit positions.
Table 9 shows a list operator precedence rules.
Table 9:
Precedence Rules
!,

Highest Precedence 












,









Lowest Precedence 
Program 1 shows how to implement an 8bit adder.
Up: Lab 5: Arithmetic Logic
Previous: 2 Lab
Copyright © 2008, Electrical Engineering Department, New Mexico Tech
Last Modified 20081010