2 Lab

1. Design the ALU using Verilog. (Make sure you deal with any unused bit combinations of the ALU_CTL lines).
2. Simulate the ALU and test different combinations of DATA and ACCA.
3. Program your ALU code into your CPLD.
4. Create another program that will call your ALU module. In this module read external inputs for ACCA and DATA as well as the ALU_CTR. Output your results on two 7-segment displays (Pinout of the MAX II micro board is shown in Figure 2).

   Figure 2: I/O map of prototyping areas