H├ęctor Erives, Ph.D., P.E.
Associate Professor
EE 231 Digital Electronics
Syllabus

Homework (Fundamentals of Digital Logic with Verilog Design)
Homework #1: 1.2, 1.6, 1.8 (Due 9/1)
Homework #2: 2.5, 2.8, 2.14, 2.20, 2.32 (Due 9/11)
Homework #3: 2.52, 2.58, 2.63, 2.66 (Due 9/18)
Homework #4: 3.1, 3.3, 3.5, 3.9, 3.17, 3.21 (Due 9/25)
Homework #5: 5.3, 5.7, 5.10, 5.13, 5.17 (Due 10/16)
Homework #6: 6.3, 6.6, 6.9, 6.12, 6.17 (Due 11/10)
Homework #7: 6.20, 6.26, 6.29, 6.32, 6.34 (Due 11/17)


Review for Exam 1
Last Modified: August 2017