EE 231 Lab 8

EE 231
Lab 8: Introduction to Clocked Sequential Circuits

Modulo 3 counter using D flip flops

The transition table for modulo 3, or divide by 3 binary counter is:

Q1	Q0	Q1⁺	Q0⁺
0	0	0	1
0	1	1	0
1	0	0	0
1	1	0	0

Table 1: Transition and output table for divide by 3 counter

Note that it generates the sequence

...... 00, 01, 10, 00, 01, 10, 00, .......

This is called a divide by three counter because it outputs a modulo 3 sequence ... 0, 1, 2, 0, 1, 2, 0 ...

The outputs of the flip flops are used as both coded states and outputs in this scheme. Note that 11 goes to 00. If the machine somehow gets in the state 11, say at power up, or from a cosmic ray, it will revert to the normal count automatically.

Build the divide by three counter designed in Prelab 8, and test it using the logic analyzer. Use a TTL clock from your breadboard to drive the counter, and verify that the operation of the circuit agrees with your timing diagram. Do not remove this design as you will need it in the last part of the lab.

Modulo four up/down counter using a programmable logic device
The AHDL language can work directly with state diagram specifications. Three example programs to do the divide by three counter are attached. Your program, to do as part of Prelab 8, can be patterned after any of the three. The third has an enable that turns the counter to wait or count. An enable could have been included in the table of the first two.

Show that your modulo four up-down counter, designed in Prelab 8, works using the logic analyzer.
Timing diagrams from the logic analyzer
Operate both counters at once. Produce the timing diagram for both on the logic analyzer simultaneously. Get a printout of the timing diagram showing that each counter operates as specified.

SUBDESIGN lab5asam
% divide by 3 counter using 2 D-flip-flops %
(
  CLOCK  :INPUT;
  Q1,Q0  :OUTPUT;
)
VARIABLE
  Q1,Q0  :DFF;    % DFF = D-flip-flop %
BEGIN
  Q1.CLK = CLOCK;
  Q0.CLK = CLOCK;

  TABLE
% current     next %
% state      state %
  Q1,Q0  =>  Q1,Q0;
   0,0   =>   0,1;
   0,1   =>   1,0;
   1,0   =>   0,0;
   1,1   =>   0,0;
  END TABLE;
END;

SUBDESIGN lab5bsam
  % divide by 3 counter using Machine of bits  %
(
        CLOCK        :INPUT;
        Q1,Q0        :OUTPUT;
)
VARIABLE
        ss: Machine of Bits (Q1,Q0)
            WITH STATES (s0=B"00",s1=B"01",s2=B"10",s3=B"11");
BEGIN
        ss.clk = clock;
        TABLE
                ss => ss;
                s0 => s1;
                s1 => s2;
                s2 => s0;
                s3 => s0;
        END TABLE;
END;


SUBDESIGN lab5csam
% divide by 3 counter - version C %
% EN enables the counter          %
(
CLOCK, EN        : INPUT;
Q1,Q0            : OUTPUT;
)
VARIABLE
        S: Machine of Bits (Q1,Q0)
            WITH STATES (ZERO=B"00",ONE=B"01",TWO=B"10",THREE=B"11");
            % in 'ZERO=B"00"' the B means binary  % 
BEGIN
        S.CLK = CLOCK;
        CASE S IS
                WHEN ZERO =>
                        IF (EN == 0) THEN S = ZERO;
                        ELSE S = ONE;
                        END IF;
                WHEN ONE =>
                        IF EN THEN S = TWO;
                        ELSE S = ONE;
                        END IF;
                WHEN TWO =>
                        IF (EN == 1) THEN S = ZERO;
                        ELSE S = TWO;
                        END IF;
                WHEN THREE =>
                        S = ZERO;
        END CASE;
END;

EE 231 Lab 8: Introduction to Clocked Sequential Circuits

EE 231
Lab 8: Introduction to Clocked Sequential Circuits