3.1 More on Verilog

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3.1 More on Verilog

3.1.1 Three-State Gates

If the control signal is 1, the output is enabled, and if the control signal is 0, the output is disabled and the gate is in high-impedance mode. There are three types of three-state gates.

**Figure 7:** Three-state gate
$\begin{figure}\begin{center} % \input{three_state.pstex_t} \end{center} \end{figure}$

bufif1(output, input, control): output equals the input if the control signal is 1, and high-impedance state,z, if the control signal is 0.
bufif0(output, input, control): the control signal is the complement of bufif1.
notif1(output, input, control): same as bufif1 except the output is the complement of the input if the control signal is 1.
notif0(output, input, control): same as bufif0 except the output is the complement of the input if the control signal is 0.

3.1.2 Logic Levels

0	logic zero, false condition
1	logic one, true condition
x	unknown logic value
z	high impedance

Next: 3.2 Verilog - Behavioral Up: 3 Supplementary Material Previous: 3 Supplementary Material