
EE 231 Digital Electronics Lab (Fall 2016)
 Syllabus

Suplement(s) Introduction to Xilinx ISE and Verilog
Constants.v
meminit.v
mem_block.v
mem_block_w_comments.v
Bounce Counter
Lab Schedule:
Date  Laboratory 
08/30 and 08/31  Lab 0: HCMOS Logic Family 
09/06 and 09/07  Lab 1: Introduction to Verilog HDL and the Xilinx ISE 
09/13 and 09/14  Lab 2: Decoders and Multiplexers 
09/20 and 09/21  Lab 3: Adder/Subtractor 
09/27 and 09/28  Lab 4: Arithmetic Logic Unit (ALU) 
10/04 and 10/05  Lab 5: Registers 
10/11 and 10/12  Lab 6: Debouncing Switches 
10/18 and 10/19  Lab 7: Reaction Timer 
10/25 and 11/26  Lab 8: Computer Control Unit (CCU)... 
11/01 and 11/02  ...Lab 8: Computer Control Unit (CCU) 
11/08 and 11/09  Lab 9: Build a Computer ... 
11/15 and 11/16  ...Lab 9: Build a Computer 
Suplements:
Many thanks to EE students William Brooks for revamping and restructuring the EE231 Lab experiments, and to Carlos Bernal and Matt Kline for testing them.
Last Modified: August 25, 2016