Dr. Aly El-Osery ee

Last Updated: November 18 2009

EE 231L: Digital Electronics Lab

(Tentative Schedule)

Grading

Number Title Dates
Lab 0 Wire Wrapping Project: Counter Board Aug. 31 and Sept. 2
Lab 1 HCMOS Logic Family Sep. 9 and 14
Lab 2 Introduction to Verilog HDL and Quartus Sep. 16 and 21
Lab 3 Decoders and Multiplexers Sep. 23 and 28
Lab 4 4-Bit Adders/Subtractor Sep. 30 and Oct. 5
Lab 5 Arithmetic Logic Unit Oct. 7 and 12
Lab 6 Debouncing Switches Oct. 14 and 19
Lab 7 Sequential Circuits Oct. 21 and 26
Lab 8 Registers Oct. 28 and Nov. 2
Lab 9 Computer Control Unit Nov. 4 and 9
Lab 9 Computer Control Unit Nov. 11 and 16
Lab 10 Build a Computer Nov. 18 and 23
Lab 11 Control System Nov. 30 and Dec. 2
Lab 12 Make-up week Dec. 7 and 9

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